RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption and More

December 8, 2020

ZURICH, Dec. 8, 2020 — RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), highlighted the organization’s incredible year of growth in a keynote today by Calista Redmond, CEO of RISC-V International, at the RISC-V Summit, which is being held virtually from Dec. 8-10, 2020. This year RISC-V International has made significant progress on technical deliverables, launched new educational programs, expanded its leadership team and membership base, and has continued to see strong commercial adoption.

“RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, SoCs, developer boards, software and tools across computing from embedded to enterprise,” said Redmond. “We’re proud of our growing global membership, which has doubled in the last year to more than 900 total members, including 215 organizations.”

In 2020 RISC-V continued to focus on driving progression and closure on standards and technical deliverables. In March, the RISC-V Processor Trace Task Group ratified the processor trace specification, a new standard trace encoder algorithm that allows engineers and developers to see exactly what instructions a core is executing, step by step. The RISC-V Technical Steering Committee (TSC) focused on implementing organizational governance practices to increase transparency. The RISC-V Architecture Test Working Group initiated a compatibility framework and tests to help developers ensure their solutions are in accordance with the specification. Additionally, RISC-V International and GlobalPlatform, the standard for secure digital services and devices, announced a partnership to help accelerate the development of open standards that simplify security design for hardware developers and enhance the security of Internet of Things (IoT) devices and processors. RISC-V anticipates the Q1 2021 public review for our Vector, Bit Manipulation, Scalar Cryptography, Packed SIMD, Secure PMP and Virtual Memory extensions. RISC-V is also creating a security response process to better respond to potential security issues and innovative cryptography extensions to enhance performance in secure deployments.

RISC-V International has cultivated alliances with 16 different regional and industry groups to ensure collaboration across all boundaries and interests. Three of these projects, which are already in motion, include: China Academy of Sciences and PLCT Lab are working on low level virtual machine (LLVM) and GNU Compiler Collection (GCC) projects for unprivileged instructions; Shakti and IIT Madras are working on architecture tests for unprivileged instructions; and the RISC-V International Open Source Laboratory (RIOS Lab) are working on both the formal model and architecture tests for privileged instructions.

In June 2020, RISC-V International appointed Mark Himelstein as CTO to work with the RISC-V technical community to understand, define and lead strategic imperatives from ISA extensions to software and from embedded to high performance computing (HPC), with all members’ interests in mind. The organization further expanded its leadership team with the appointment of Kim McMahon as Director of Marketing to increase the visibility of RISC-V and amplify the growing industry momentum of our member community. RISC-V International also announced the first class of RISC-V Ambassadors this year. Ambassadors are RISC-V technical experts from around the world who work together with RISC-V to engage engineers around the world in technical forums.

Said Himelstein: “RISC-V has been laser focused on ratifying extensions, identifying  and addressing opportunities and gaps, and expanding collaboration and development across markets to strengthen the community and access to RISC-V resources. In 2020 we’ve expanded the number of technical groups, forged new alliances and rolled out new educational programs to help accomplish this goal, and will continue to double down on these efforts to help fuel volume deployments of RISC-V in the coming years.”

RISC-V International has launched three new learning programs including the RISC-V Training Partner Program, Learn online, and university alliances to extend the breadth and reach of RISC-V knowledge, provide opportunities for a broader audience to teach and learn, and engage the community to achieve expertise in the critical areas needed for a healthy ecosystem. One of the courses that was recently unveiled is the Imagination University Programme (IUP) course “RVfpga: Understanding Computer Architecture.” The course is currently available in English, and a Chinese version will be available in early 2021. Students and developers interested in RISC-V can also check out more than 30 educational courses on RISC-V offered from universities and other educational providers from around the world.

This year the RISC-V community has continued to contribute to RISC-V projects, collaborate together and commercialize RISC-V hardware and software solutions. RISC-V also launched the RISC-V Exchange with more than 124 RISC-V cores and SoCs and Developer Boards along with 129 RISC-V software applications and tools.

Notable examples of RISC-V adoption in 2020:

●        Alibaba unveiled its RV64GCV core that will be used for its Xuantie 910 processor aimed at cloud and edge servers.

●       Andes released new superscalar multicore processors and processors with Level-2 (L2) cache controller.

●        BBC Learning and Tynker released the BBC Doctor Who HiFive Inventor to engage the next generation of coders.

●        Bluespec, Inc. unveiled RISC-V Explorer, a fast, free and accurate way to evaluate RISC-V cores.

●        CHIPS Alliance announced new enhancements to the SweRV Core EH2 and SweRV Core EL2.

●        Codasip released Bk7, optimized for domain-specific applications such as security and real-time AI processing, especially where embedded Linux is required.

●        De-RISC developed the first version of its De-RISC MPSoC platform and Performance Monitoring Unit as part of its effort to create a RISC-V platform for the aerospace market.

●        Esperanto Technologies unveiled an accelerator chip for large-scale machine learning applications employing over 1000 RISC-V cores.

●        Espressif launched cost-effective microcontroller with Wi-Fi and Bluetooth LE 5.0 connectivity for secure IoT applications.

●        GreenWaves Technologies announced its ultra-low power GAP9 hearables platform that enables scene-aware active noise cancellation and neural network-based noise reduction.

●        Huami released a new AI chip for biometric wearables.

●        IAR Systems partnered with GigaDevice to deliver powerful development tools for GigaDevice’s RISC-V based microcontrollers.

●        IAR Systems and SiFive enhanced support for the SiFive Insight solution in IAR Embedded Workbench to bring leading debug and trace capabilities to the RISC-V community.

●        Imagination Technologies partnered with RIOS Laboratory to enable RIOS Lab to build a complete development platform and open-source ecosystem for RISC-V single-board computers.

●        Imperas Software debuted a reference model with UVM encapsulation for RISC-V verification.

●        Lynred and GreenWaves Technologies collaborated on a new Occupancy Management Reference Platform for people counting sensors.

●        MEEP developed Coyote, a performance modeling tool to provide an execution-driven simulation environment for multicore RISC-V systems with multi-level memory hierarchies.

●        Mentor collaborated with Imperas on RISC-V core RTL coverage driven design verification analysis.

●        Microchip Technology announced a RISC-V-based SoC FPGA development kit to accelerate customer design deployment and commercial adoption across a variety of industries.

●        Micro Magic, Inc. unveiled a 64-bit RISC-V core achieving 5GHz and 13,000 CoreMarks at 1.1V.

●        NeuLinker selected Codasip’s Bk5 core and the Codasip Studio customization toolset for its security and AI-powering solutions.

●        OneSpin announced it is contributing its processor integrity solutions for the German government’s ZuSE-Scale4Edge project to assure integrity of edge computing processors.

●        OpenHW Group implemented Imperas RISC-V reference models for coverage driven verification of open source CORE-V processor IP cores.

●        PINE64 unveiled the Pinecil TS100 compatible soldering iron.

●        SiFive introduced HiFive Unmatched! to make it easy for developers to build a RISC-V PC.

●        Telink Semiconductor announced its TLSR9r SoC series for wireless audio, wearable devices and other cutting-edge IoT applications.

●        The European Processor Initiative finalized the first version of its RISC-V accelerator architecture, named EPAC.

●        Think Silicon introduced new inference micro GPU architecture suitable for AI-Vision and graphics tasks.

●        University of Chinese Academy of Sciences (UCAS) developed NutShell, a 64-bit SoC which operates at up to 200MHz and can run Linux.

In March 2020, RISC-V International was incorporated in Switzerland. As part of the move, RISC-V shifted to a new, more inclusive membership structure. RISC-V International is a truly global organization, with 31 percent of its membership base in North America, 33 percent in Europe and 37 percent in Asia-Pacific. To engage with the global RISC-V community, RISC-V International has participated in nearly 40 events ranging from Embedded World and HiPEAC in Europe to DAC and Open Source Summit in North America to regional events in China and Taiwan.

To learn more about the free and open RISC-V ISA, please visit: https://riscv.org. To become a member of RISC-V International, please visit: https://riscv.org/membership/.

About RISC-V International

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, RISC-V International comprises more than 900 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

RISC-V International, a non-profit organization controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of RISC-V International have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.


Source: RISC-V International

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

What’s New in HPC Research: Galaxies, Fugaku, Electron Microscopes & More

January 25, 2021

In this regular feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

Red Hat’s Disruption of CentOS Unleashes Storm of Dissent

January 22, 2021

Five weeks after angering much of the CentOS Linux developer community by unveiling controversial changes to the no-cost CentOS operating system, Red Hat has unveiled alternatives for affected users that give them severa Read more…

By Todd R. Weiss

China Unveils First 7nm Chip: Big Island

January 22, 2021

Shanghai Tianshu Zhaoxin Semiconductor Co. is claiming China’s first 7-nanometer chip, described as a leading-edge, general-purpose cloud computing chip based on a proprietary GPU architecture. Dubbed “Big Island Read more…

By George Leopold

HiPEAC Keynote: In-Memory Computing Steps Closer to Practical Reality

January 21, 2021

Pursuit of in-memory computing has long been an active area with recent progress showing promise. Just how in-memory computing works, how close it is to practical application, and what are some of the key opportunities a Read more…

By John Russell

HiPEAC’s Vision for a New Cyber Era, a ‘Continuum of Computing’

January 21, 2021

Earlier this week (Jan. 19), HiPEAC — the European Network on High Performance and Embedded Architecture and Compilation — published the 8th edition of the HiPEAC Vision, detailing an increasingly interconnected computing landscape where complex tasks are carried out across multiple... Read more…

By Tiffany Trader

AWS Solution Channel

Fire Dynamics Simulation CFD workflow on AWS

Modeling fires is key for many industries, from the design of new buildings, defining evacuation procedures for trains, planes and ships, and even the spread of wildfires. Read more…

Supercomputers Assist Hunt for Mysterious Axion Particle

January 21, 2021

In the 1970s, scientists theorized the existence of axions: particles born in the hearts of stars that, when exposed to a magnetic field, become light particles, and which may even comprise dark matter. To date, however, Read more…

By Oliver Peckham

Red Hat’s Disruption of CentOS Unleashes Storm of Dissent

January 22, 2021

Five weeks after angering much of the CentOS Linux developer community by unveiling controversial changes to the no-cost CentOS operating system, Red Hat has un Read more…

By Todd R. Weiss

HiPEAC Keynote: In-Memory Computing Steps Closer to Practical Reality

January 21, 2021

Pursuit of in-memory computing has long been an active area with recent progress showing promise. Just how in-memory computing works, how close it is to practic Read more…

By John Russell

HiPEAC’s Vision for a New Cyber Era, a ‘Continuum of Computing’

January 21, 2021

Earlier this week (Jan. 19), HiPEAC — the European Network on High Performance and Embedded Architecture and Compilation — published the 8th edition of the HiPEAC Vision, detailing an increasingly interconnected computing landscape where complex tasks are carried out across multiple... Read more…

By Tiffany Trader

Saudi Aramco Unveils Dammam 7, Its New Top Ten Supercomputer

January 21, 2021

By revenue, oil and gas giant Saudi Aramco is one of the largest companies in the world, and it has historically employed commensurate amounts of supercomputing Read more…

By Oliver Peckham

President-elect Biden Taps Eric Lander and Deep Team on Science Policy

January 19, 2021

Last Friday U.S. President-elect Joe Biden named The Broad Institute founding director and president Eric Lander as his science advisor and as director of the Office of Science and Technology Policy. Lander, 63, is a mathematician by training and distinguished life sciences... Read more…

By John Russell

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Intel ‘Ice Lake’ Server Chips in Production, Set for Volume Ramp This Quarter

January 12, 2021

Intel Corp. used this week’s virtual CES 2021 event to reassert its dominance of the datacenter with the formal roll out of its next-generation server chip, the 10nm Xeon Scalable processor that targets AI and HPC workloads. The third-generation “Ice Lake” family... Read more…

By George Leopold

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

December 8, 2020

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in... Read more…

By Oliver Peckham

Azure Scaled to Record 86,400 Cores for Molecular Dynamics

November 20, 2020

A new record for HPC scaling on the public cloud has been achieved on Microsoft Azure. Led by Dr. Jer-Ming Chia, the cloud provider partnered with the Beckman I Read more…

By Oliver Peckham

NICS Unleashes ‘Kraken’ Supercomputer

April 4, 2008

A Cray XT4 supercomputer, dubbed Kraken, is scheduled to come online in mid-summer at the National Institute for Computational Sciences (NICS). The soon-to-be petascale system, and the resulting NICS organization, are the result of an NSF Track II award of $65 million to the University of Tennessee and its partners to provide next-generation supercomputing for the nation's science community. Read more…

Is the Nvidia A100 GPU Performance Worth a Hardware Upgrade?

October 16, 2020

Over the last decade, accelerators have seen an increasing rate of adoption in high-performance computing (HPC) platforms, and in the June 2020 Top500 list, eig Read more…

By Hartwig Anzt, Ahmad Abdelfattah and Jack Dongarra

Aurora’s Troubles Move Frontier into Pole Exascale Position

October 1, 2020

Intel’s 7nm node delay has raised questions about the status of the Aurora supercomputer that was scheduled to be stood up at Argonne National Laboratory next year. Aurora was in the running to be the United States’ first exascale supercomputer although it was on a contemporaneous timeline with... Read more…

By Tiffany Trader

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Leading Solution Providers

Contributors

Top500: Fugaku Keeps Crown, Nvidia’s Selene Climbs to #5

November 16, 2020

With the publication of the 56th Top500 list today from SC20's virtual proceedings, Japan's Fugaku supercomputer – now fully deployed – notches another win, Read more…

By Tiffany Trader

Texas A&M Announces Flagship ‘Grace’ Supercomputer

November 9, 2020

Texas A&M University has announced its next flagship system: Grace. The new supercomputer, named for legendary programming pioneer Grace Hopper, is replacing the Ada system (itself named for mathematician Ada Lovelace) as the primary workhorse for Texas A&M’s High Performance Research Computing (HPRC). Read more…

By Oliver Peckham

At Oak Ridge, ‘End of Life’ Sometimes Isn’t

October 31, 2020

Sometimes, the old dog actually does go live on a farm. HPC systems are often cursed with short lifespans, as they are continually supplanted by the latest and Read more…

By Oliver Peckham

Gordon Bell Special Prize Goes to Massive SARS-CoV-2 Simulations

November 19, 2020

2020 has proven a harrowing year – but it has produced remarkable heroes. To that end, this year, the Association for Computing Machinery (ACM) introduced the Read more…

By Oliver Peckham

Nvidia and EuroHPC Team for Four Supercomputers, Including Massive ‘Leonardo’ System

October 15, 2020

The EuroHPC Joint Undertaking (JU) serves as Europe’s concerted supercomputing play, currently comprising 32 member states and billions of euros in funding. I Read more…

By Oliver Peckham

Intel Xe-HP GPU Deployed for Aurora Exascale Development

November 17, 2020

At SC20, Intel announced that it is making its Xe-HP high performance discrete GPUs available to early access developers. Notably, the new chips have been deplo Read more…

By Tiffany Trader

Nvidia-Arm Deal a Boon for RISC-V?

October 26, 2020

The $40 billion blockbuster acquisition deal that will bring chipmaker Arm into the Nvidia corporate family could provide a boost for the competing RISC-V architecture. As regulators in the U.S., China and the European Union begin scrutinizing the impact of the blockbuster deal on semiconductor industry competition and innovation, the deal has at the very least... Read more…

By George Leopold

HPE, AMD and EuroHPC Partner for Pre-Exascale LUMI Supercomputer

October 21, 2020

Not even a week after Nvidia announced that it would be providing hardware for the first four of the eight planned EuroHPC systems, HPE and AMD are announcing a Read more…

By Oliver Peckham

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This