SC16 Announces Best Paper Nominees

September 21, 2016

Sept. 21 — Out of 442 technical papers submitted to SC16, only 81 were accepted and of these, seven have been nominated for the conference’s Best Paper Award. One of the best paper candidates also is a finalist for the ACM Gordon Bell Prize, which will be presented at SC16.

Overall, the conference had an 18.3 percent acceptance rate for papers, which covered nine different focus areas. The areas are Applications; Algorithms; Architectures and Networks; Clouds and Distributed Computing; Data Analytics, Visualization and Storage; Performance Measurement, Modeling and Tools; Programming Systems; State of the Practice; and System Software.

“Within each of the major topical areas, individual members of the program committee nominate the submissions that they consider to have the strongest technical innovation and potential for impact,” says Rich Vuduc of Georgia Tech, SC16 Technical Papers Vice Chair. “The committee then discusses these candidates in order to identify up to one best paper and one best student paper within the area to be a finalist. A separate committee will select winners during SC16 in November.”

The following are this year’s Best Paper Award nominees:

Toward Green Aviation with Python at Petascale (also a Gordon Bell Prize Finalist), Peter Vincent, Freddie Witherden, Brian Vermeire, Jin Seok Park, and Arvind Iyer, all of Imperial College London.

Accurate simulation of unsteady turbulent flow is critical for improved design of ‘greener’ aircraft that are quieter and more fuel-efficient. We demonstrate application of PyFR, a Python based computational fluid dynamics solver, to petascale simulation of such flow problems. Rationale behind algorithmic choices, which offer increased levels of accuracy and enable sustained computation at up to 58 percent of peak DP-FLOP/s on unstructured grids, will be discussed in the context of modern hardware.

A range of software innovations also will be detailed, including use of runtime code generation, which enables PyFR to efficiently target multiple platforms, including heterogeneous systems, via a single implementation. Finally, results will be presented from a full-scale simulation of flow over a low-pressure turbine blade cascade, along with weak/strong scaling statistics from the Piz Daint and Titan supercomputers, and performance data demonstrating sustained computation at up to 13.7 DP-PFLOP/s.

The Mont-Blanc Prototype: An Alternative Approach for HPC Systems, Nikola Rajovic, Barcelona Supercomputing Center; Alejandro Rico, ARM; Filippo Mantovani, Barcelona Supercomputing Center; Daniel Ruiz, Barcelona Supercomputing Center; Josep Oriol Vilarrubi, Barcelona Supercomputing Center; Constantino Gomez, Barcelona Supercomputing Center; Luna Backes, Barcelona Supercomputing Center; Diego Nieto, Barcelona Supercomputing Center; Harald Servat, Barcelona Supercomputing Center; Xavier Martorell, Barcelona Supercomputing Center; Jesus Labarta, Barcelona Supercomputing Center; Eduard Ayguade, Barcelona Supercomputing Center; Chris Adeniyi-Jones, ARM; Said Derradji, Bull; Herve Gloaguen, Bull; Piero Lanucara, CINECA; Nico Sanna, CINECA; Jean-François Méhaut, Grenoble Alpes University; Kevin Pouget, Grenoble Alpes University; Brice Videau, Grenoble Alpes University; Eric Boyer, GENCI; Momme Allalen, Leibniz Supercomputing Centre; Axel Auweter, Leibniz Supercomputing Centre; David Brayford, Leibniz Supercomputing Centre; Daniele Tafani, Leibniz Supercomputing Centre; Volker Weinberg, Leibniz Supercomputing Centre; Dirk Brömmel, Forschungszentrum Juelich; Rene Halver, Forschungszentrum Juelich; Jan H. Meinke, Forschungszentrum Juelich; Ramon Beivide, University of Cantabria; Mariano Benito, University of Cantabria; Enrique Vallejo, University of Cantabria; Mateo Valero, Barcelona Supercomputing Center; Alex Ramirez, NVIDIA Corporation.

HPC systems are usually designed using the state-of-the-art devices. On the otherhand, the much larger embedded and mobile market allows for rapid development of IP blocks and provides more flexibility in designing an application-specific SoC, in turn, providing the possibility in balancing performance, energy-efficiency and cost.

We advocate for alternative HPC systems to be built from such commodity IP blocks currently used in embedded and mobile SoCs. As a first demonstration of such an approach, we present the Mont-Blanc prototype; the first HPC system built with commodity SoCs, memories, and NICs from the embedded and mobile domain, and off-the-shelf HPC networking, storage, cooling, using standard integration solutions.

In this paper, we present the system’s architecture and evaluate both performance and energy-efficiency. Further, we compare the system’s abilities against a production-level supercomputer. Finally, we discuss parallel scalability and estimate the maximum parallel scalability point of this approach.

Automating Wavefront Parallelization for Sparse Matrix Codes, Anand  Venkat, University of Utah; Mahdi Soltan Mohammadi, University of Arizona; Jongsoo Park, Intel Corporation; Hongbo Rong, Intel Corporation; Rajkishore Barik, Intel Corporation; Michelle Mills Strout, University of Arizona; Mary Hall, University of Utah.

This paper presents a compiler and runtime framework for parallelizing sparse matrix computations that have loop-carried dependences. Our approach automatically generates a runtime inspector to collect data dependence information and achieves wavefront parallelization of the computation, where iterations within a wavefront execute in parallel, and synchronization is required across wavefronts. A key contribution of this paper involves dependence simplification, which reduces the time and space overhead of the inspector.

This is implemented within a polyhedral compiler framework, extended for sparse matrix codes. Results demonstrate the feasibility of using automatically-generated inspectors and executors to optimize ILU factorization and symmetric Gauss-Seidel relaxations, which are part of the Preconditioned Conjugate Gradient (PCG) computation. Our implementation achieves a median speedup of 2.97x and 2.82x over the reference sequential PCG implementation and PCG parallelized with the Intel Math Kernel Library (MKL) respectively and are within 7 percent of the median performance of manually tuned code.

Failure Detection and Propagation in HPC Systems, George Bosilca, University of Tennessee; Aurelien Bouteiller, University of Tennessee; Amina Guermouche University of Tennessee; Thomas Herault, University of Tennessee; Yves Robert, ENS Lyon; Pierre Sens, LIP6 Paris; Jack Dongarra, University of Tennessee.

Building an infrastructure for exascale applications requires, in addition to many other key components, a stable and efficient failure detector. This paper describes the design and evaluation of a robust failure detector, able to maintain and distribute the correct list of alive resources within proven and scalable bounds.

The detection and distribution of the fault information follow different overlay topologies that together guarantee minimal disturbance to the applications. A virtual observation ring minimizes the overhead by allowing each node to be observed by another single node, providing an unobtrusive behavior.

The propagation stage is using a non-uniform variant of a reliable broadcast over a circulant graph overlay network, and guarantees a logarithmic fault propagation. Extensive simulations, together with experiments on the ORNL Titan supercomputer, show that the algorithm performs extremely well and exhibits all the desired properties of an exascale-ready algorithm.

Performance Modeling of In Situ Rendering, Matthew Larsen, University of Oregon; Cyrus Harrison, Lawrence Livermore National Laboratory; James Kress, University of Oregon; Dave Pugmire, Oak Ridge National Laboratory; Jeremy Meredith, Oak Ridge National Laboratory; Hank Childs, University of Oregon.

With the push to exascale, in situ visualization and analysis will continue to play an important role in HPC. Tightly coupling in situ visualization with simulations constrains resources for both, and these constraints force a complex balance of trade-offs. A performance model that provides an a priori answer for the cost of using an in situ approach for a given task would assist in managing the trade-offs between simulation and visualization resources.

In this work, we present new statistical performance models, based on algorithmic complexity, that accurately predict the run-time cost of a set of representative rendering algorithms, an essential in situ visualization task. To train and validate the models, we conduct a performance study of an MPI+X rendering infrastructure used in situ with three HPC simulation applications. We then explore feasibility issues using the model for selected in situ rendering questions.

An Efficient and Scalable Algorithmic Method for Generating Large-Scale Random Graphs, Maksudul Alam, Virginia Polytechnic Institute and State University; Maleq Khan, Virginia Polytechnic Institute and State University; Anil Vullikanti, Virginia Polytechnic Institute and State University; Madhav Marathe, Virginia Polytechnic Institute and State University.

Many real-world systems are modeled and analyzed using various random network models. For realistic analysis, models must incorporate relevant properties such as degree distribution and clustering coefficient. Many models, such as the Chung-Lu, stochastic Kronecker, stochastic blockmodels (SBM), and block two-level Erdos-Renyi (BTER) models have been devised to capture those properties.

However, the generative algorithms for these models are mostly sequential and take a prohibitively long time. In this paper, we present a novel time and space efficient algorithm for the Chung-Lu model requiring O(m) time and O(Λ) space, where m and Λ are the number of edges and distinct degrees.

We also present a distributed-memory parallel algorithm with P processors requiring O(m/P+Λ+P) time and O(Λ) space. Finally, we extend our algorithms for two other popular models: SBM and BTER. These algorithms are highly scalable. Generating a power-law network with 250 billion edges takes only 12 seconds using 1024 processors.

Daino: A High-Level Framework for Parallel and Efficient AMR on GPUs, Mohamed Wahib Attia, RIKEN; Naoya Maruyama, RIKEN; and Takayuki Aoki, Tokyo Institute of Technology.

Adaptive Mesh Refinement methods reduce computational requirements of problems by increasing resolution for only areas of interest. However, in practice, efficient AMR implementations are difficult considering that the mesh hierarchy management must be optimized for the underlying hardware. Architecture complexity of GPUs can render efficient AMR to be particularly  challenging in GPU-accelerated supercomputers.

This paper presents a compiler-based high-level framework that can automatically transform serial uniform mesh code annotated by the user into parallel adaptive mesh code optimized for GPU-accelerated supercomputers. We also present a method for empirical analysis of a uniform mesh to project an upper-bound on achievable speedup of a GPU-optimized AMR code.

We show experimental results on three production applications. The speedup of code generated by our framework  is comparable to hand-written AMR code while achieving good and weak scaling up to 1000 GPUs.


Source: SC16

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Red Hat’s Disruption of CentOS Unleashes Storm of Dissent

January 22, 2021

Five weeks after angering much of the CentOS Linux developer community by unveiling controversial changes to the no-cost CentOS operating system, Red Hat has unveiled alternatives for affected users that give them severa Read more…

By Todd R. Weiss

China Unveils First 7nm Chip: Big Island

January 22, 2021

Shanghai Tianshu Zhaoxin Semiconductor Co. is claiming China’s first 7-nanometer chip, described as a leading-edge, general-purpose cloud computing chip based on a proprietary GPU architecture. Dubbed “Big Island Read more…

By George Leopold

HiPEAC Keynote: In-Memory Computing Steps Closer to Practical Reality

January 21, 2021

Pursuit of in-memory computing has long been an active area with recent progress showing promise. Just how in-memory computing works, how close it is to practical application, and what are some of the key opportunities a Read more…

By John Russell

HiPEAC’s Vision for a New Cyber Era, a ‘Continuum of Computing’

January 21, 2021

Earlier this week (Jan. 19), HiPEAC — the European Network on High Performance and Embedded Architecture and Compilation — published the 8th edition of the HiPEAC Vision, detailing an increasingly interconnected computing landscape where complex tasks are carried out across multiple... Read more…

By Tiffany Trader

Supercomputers Assist Hunt for Mysterious Axion Particle

January 21, 2021

In the 1970s, scientists theorized the existence of axions: particles born in the hearts of stars that, when exposed to a magnetic field, become light particles, and which may even comprise dark matter. To date, however, Read more…

By Oliver Peckham

AWS Solution Channel

Fire Dynamics Simulation CFD workflow on AWS

Modeling fires is key for many industries, from the design of new buildings, defining evacuation procedures for trains, planes and ships, and even the spread of wildfires. Read more…

Researchers Train Fluid Dynamics Neural Networks on Supercomputers

January 21, 2021

Fluid dynamics simulations are critical for applications ranging from wind turbine design to aircraft optimization. Running these simulations through direct numerical simulations, however, is computationally costly. Many Read more…

By Oliver Peckham

Red Hat’s Disruption of CentOS Unleashes Storm of Dissent

January 22, 2021

Five weeks after angering much of the CentOS Linux developer community by unveiling controversial changes to the no-cost CentOS operating system, Red Hat has un Read more…

By Todd R. Weiss

HiPEAC Keynote: In-Memory Computing Steps Closer to Practical Reality

January 21, 2021

Pursuit of in-memory computing has long been an active area with recent progress showing promise. Just how in-memory computing works, how close it is to practic Read more…

By John Russell

HiPEAC’s Vision for a New Cyber Era, a ‘Continuum of Computing’

January 21, 2021

Earlier this week (Jan. 19), HiPEAC — the European Network on High Performance and Embedded Architecture and Compilation — published the 8th edition of the HiPEAC Vision, detailing an increasingly interconnected computing landscape where complex tasks are carried out across multiple... Read more…

By Tiffany Trader

Saudi Aramco Unveils Dammam 7, Its New Top Ten Supercomputer

January 21, 2021

By revenue, oil and gas giant Saudi Aramco is one of the largest companies in the world, and it has historically employed commensurate amounts of supercomputing Read more…

By Oliver Peckham

President-elect Biden Taps Eric Lander and Deep Team on Science Policy

January 19, 2021

Last Friday U.S. President-elect Joe Biden named The Broad Institute founding director and president Eric Lander as his science advisor and as director of the Office of Science and Technology Policy. Lander, 63, is a mathematician by training and distinguished life sciences... Read more…

By John Russell

Pat Gelsinger Returns to Intel as CEO

January 14, 2021

The Intel board of directors has appointed a new CEO. Intel alum Pat Gelsinger is leaving his post as CEO of VMware to rejoin the company that he parted ways with 11 years ago. Gelsinger will succeed Bob Swan, who will remain CEO until Feb. 15. Gelsinger previously spent 30 years... Read more…

By Tiffany Trader

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Intel ‘Ice Lake’ Server Chips in Production, Set for Volume Ramp This Quarter

January 12, 2021

Intel Corp. used this week’s virtual CES 2021 event to reassert its dominance of the datacenter with the formal roll out of its next-generation server chip, the 10nm Xeon Scalable processor that targets AI and HPC workloads. The third-generation “Ice Lake” family... Read more…

By George Leopold

Esperanto Unveils ML Chip with Nearly 1,100 RISC-V Cores

December 8, 2020

At the RISC-V Summit today, Art Swift, CEO of Esperanto Technologies, announced a new, RISC-V based chip aimed at machine learning and containing nearly 1,100 low-power cores based on the open-source RISC-V architecture. Esperanto Technologies, headquartered in... Read more…

By Oliver Peckham

Julia Update: Adoption Keeps Climbing; Is It a Python Challenger?

January 13, 2021

The rapid adoption of Julia, the open source, high level programing language with roots at MIT, shows no sign of slowing according to data from Julialang.org. I Read more…

By John Russell

Azure Scaled to Record 86,400 Cores for Molecular Dynamics

November 20, 2020

A new record for HPC scaling on the public cloud has been achieved on Microsoft Azure. Led by Dr. Jer-Ming Chia, the cloud provider partnered with the Beckman I Read more…

By Oliver Peckham

NICS Unleashes ‘Kraken’ Supercomputer

April 4, 2008

A Cray XT4 supercomputer, dubbed Kraken, is scheduled to come online in mid-summer at the National Institute for Computational Sciences (NICS). The soon-to-be petascale system, and the resulting NICS organization, are the result of an NSF Track II award of $65 million to the University of Tennessee and its partners to provide next-generation supercomputing for the nation's science community. Read more…

Is the Nvidia A100 GPU Performance Worth a Hardware Upgrade?

October 16, 2020

Over the last decade, accelerators have seen an increasing rate of adoption in high-performance computing (HPC) platforms, and in the June 2020 Top500 list, eig Read more…

By Hartwig Anzt, Ahmad Abdelfattah and Jack Dongarra

Aurora’s Troubles Move Frontier into Pole Exascale Position

October 1, 2020

Intel’s 7nm node delay has raised questions about the status of the Aurora supercomputer that was scheduled to be stood up at Argonne National Laboratory next year. Aurora was in the running to be the United States’ first exascale supercomputer although it was on a contemporaneous timeline with... Read more…

By Tiffany Trader

10nm, 7nm, 5nm…. Should the Chip Nanometer Metric Be Replaced?

June 1, 2020

The biggest cool factor in server chips is the nanometer. AMD beating Intel to a CPU built on a 7nm process node* – with 5nm and 3nm on the way – has been i Read more…

By Doug Black

Programming the Soon-to-Be World’s Fastest Supercomputer, Frontier

January 5, 2021

What’s it like designing an app for the world’s fastest supercomputer, set to come online in the United States in 2021? The University of Delaware’s Sunita Chandrasekaran is leading an elite international team in just that task. Chandrasekaran, assistant professor of computer and information sciences, recently was named... Read more…

By Tracey Bryant

Leading Solution Providers

Contributors

Top500: Fugaku Keeps Crown, Nvidia’s Selene Climbs to #5

November 16, 2020

With the publication of the 56th Top500 list today from SC20's virtual proceedings, Japan's Fugaku supercomputer – now fully deployed – notches another win, Read more…

By Tiffany Trader

Texas A&M Announces Flagship ‘Grace’ Supercomputer

November 9, 2020

Texas A&M University has announced its next flagship system: Grace. The new supercomputer, named for legendary programming pioneer Grace Hopper, is replacing the Ada system (itself named for mathematician Ada Lovelace) as the primary workhorse for Texas A&M’s High Performance Research Computing (HPRC). Read more…

By Oliver Peckham

At Oak Ridge, ‘End of Life’ Sometimes Isn’t

October 31, 2020

Sometimes, the old dog actually does go live on a farm. HPC systems are often cursed with short lifespans, as they are continually supplanted by the latest and Read more…

By Oliver Peckham

Gordon Bell Special Prize Goes to Massive SARS-CoV-2 Simulations

November 19, 2020

2020 has proven a harrowing year – but it has produced remarkable heroes. To that end, this year, the Association for Computing Machinery (ACM) introduced the Read more…

By Oliver Peckham

Nvidia and EuroHPC Team for Four Supercomputers, Including Massive ‘Leonardo’ System

October 15, 2020

The EuroHPC Joint Undertaking (JU) serves as Europe’s concerted supercomputing play, currently comprising 32 member states and billions of euros in funding. I Read more…

By Oliver Peckham

Intel Xe-HP GPU Deployed for Aurora Exascale Development

November 17, 2020

At SC20, Intel announced that it is making its Xe-HP high performance discrete GPUs available to early access developers. Notably, the new chips have been deplo Read more…

By Tiffany Trader

Nvidia-Arm Deal a Boon for RISC-V?

October 26, 2020

The $40 billion blockbuster acquisition deal that will bring chipmaker Arm into the Nvidia corporate family could provide a boost for the competing RISC-V architecture. As regulators in the U.S., China and the European Union begin scrutinizing the impact of the blockbuster deal on semiconductor industry competition and innovation, the deal has at the very least... Read more…

By George Leopold

HPE, AMD and EuroHPC Partner for Pre-Exascale LUMI Supercomputer

October 21, 2020

Not even a week after Nvidia announced that it would be providing hardware for the first four of the eight planned EuroHPC systems, HPE and AMD are announcing a Read more…

By Oliver Peckham

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This