Sept. 21 — Out of 442 technical papers submitted to SC16, only 81 were accepted and of these, seven have been nominated for the conference’s Best Paper Award. One of the best paper candidates also is a finalist for the ACM Gordon Bell Prize, which will be presented at SC16.
Overall, the conference had an 18.3 percent acceptance rate for papers, which covered nine different focus areas. The areas are Applications; Algorithms; Architectures and Networks; Clouds and Distributed Computing; Data Analytics, Visualization and Storage; Performance Measurement, Modeling and Tools; Programming Systems; State of the Practice; and System Software.
“Within each of the major topical areas, individual members of the program committee nominate the submissions that they consider to have the strongest technical innovation and potential for impact,” says Rich Vuduc of Georgia Tech, SC16 Technical Papers Vice Chair. “The committee then discusses these candidates in order to identify up to one best paper and one best student paper within the area to be a finalist. A separate committee will select winners during SC16 in November.”
The following are this year’s Best Paper Award nominees:
Toward Green Aviation with Python at Petascale (also a Gordon Bell Prize Finalist), Peter Vincent, Freddie Witherden, Brian Vermeire, Jin Seok Park, and Arvind Iyer, all of Imperial College London.
Accurate simulation of unsteady turbulent flow is critical for improved design of ‘greener’ aircraft that are quieter and more fuel-efficient. We demonstrate application of PyFR, a Python based computational fluid dynamics solver, to petascale simulation of such flow problems. Rationale behind algorithmic choices, which offer increased levels of accuracy and enable sustained computation at up to 58 percent of peak DP-FLOP/s on unstructured grids, will be discussed in the context of modern hardware.
A range of software innovations also will be detailed, including use of runtime code generation, which enables PyFR to efficiently target multiple platforms, including heterogeneous systems, via a single implementation. Finally, results will be presented from a full-scale simulation of flow over a low-pressure turbine blade cascade, along with weak/strong scaling statistics from the Piz Daint and Titan supercomputers, and performance data demonstrating sustained computation at up to 13.7 DP-PFLOP/s.
The Mont-Blanc Prototype: An Alternative Approach for HPC Systems, Nikola Rajovic, Barcelona Supercomputing Center; Alejandro Rico, ARM; Filippo Mantovani, Barcelona Supercomputing Center; Daniel Ruiz, Barcelona Supercomputing Center; Josep Oriol Vilarrubi, Barcelona Supercomputing Center; Constantino Gomez, Barcelona Supercomputing Center; Luna Backes, Barcelona Supercomputing Center; Diego Nieto, Barcelona Supercomputing Center; Harald Servat, Barcelona Supercomputing Center; Xavier Martorell, Barcelona Supercomputing Center; Jesus Labarta, Barcelona Supercomputing Center; Eduard Ayguade, Barcelona Supercomputing Center; Chris Adeniyi-Jones, ARM; Said Derradji, Bull; Herve Gloaguen, Bull; Piero Lanucara, CINECA; Nico Sanna, CINECA; Jean-François Méhaut, Grenoble Alpes University; Kevin Pouget, Grenoble Alpes University; Brice Videau, Grenoble Alpes University; Eric Boyer, GENCI; Momme Allalen, Leibniz Supercomputing Centre; Axel Auweter, Leibniz Supercomputing Centre; David Brayford, Leibniz Supercomputing Centre; Daniele Tafani, Leibniz Supercomputing Centre; Volker Weinberg, Leibniz Supercomputing Centre; Dirk Brömmel, Forschungszentrum Juelich; Rene Halver, Forschungszentrum Juelich; Jan H. Meinke, Forschungszentrum Juelich; Ramon Beivide, University of Cantabria; Mariano Benito, University of Cantabria; Enrique Vallejo, University of Cantabria; Mateo Valero, Barcelona Supercomputing Center; Alex Ramirez, NVIDIA Corporation.
HPC systems are usually designed using the state-of-the-art devices. On the otherhand, the much larger embedded and mobile market allows for rapid development of IP blocks and provides more flexibility in designing an application-specific SoC, in turn, providing the possibility in balancing performance, energy-efficiency and cost.
We advocate for alternative HPC systems to be built from such commodity IP blocks currently used in embedded and mobile SoCs. As a first demonstration of such an approach, we present the Mont-Blanc prototype; the first HPC system built with commodity SoCs, memories, and NICs from the embedded and mobile domain, and off-the-shelf HPC networking, storage, cooling, using standard integration solutions.
In this paper, we present the system’s architecture and evaluate both performance and energy-efficiency. Further, we compare the system’s abilities against a production-level supercomputer. Finally, we discuss parallel scalability and estimate the maximum parallel scalability point of this approach.
Automating Wavefront Parallelization for Sparse Matrix Codes, Anand Venkat, University of Utah; Mahdi Soltan Mohammadi, University of Arizona; Jongsoo Park, Intel Corporation; Hongbo Rong, Intel Corporation; Rajkishore Barik, Intel Corporation; Michelle Mills Strout, University of Arizona; Mary Hall, University of Utah.
This paper presents a compiler and runtime framework for parallelizing sparse matrix computations that have loop-carried dependences. Our approach automatically generates a runtime inspector to collect data dependence information and achieves wavefront parallelization of the computation, where iterations within a wavefront execute in parallel, and synchronization is required across wavefronts. A key contribution of this paper involves dependence simplification, which reduces the time and space overhead of the inspector.
This is implemented within a polyhedral compiler framework, extended for sparse matrix codes. Results demonstrate the feasibility of using automatically-generated inspectors and executors to optimize ILU factorization and symmetric Gauss-Seidel relaxations, which are part of the Preconditioned Conjugate Gradient (PCG) computation. Our implementation achieves a median speedup of 2.97x and 2.82x over the reference sequential PCG implementation and PCG parallelized with the Intel Math Kernel Library (MKL) respectively and are within 7 percent of the median performance of manually tuned code.
Failure Detection and Propagation in HPC Systems, George Bosilca, University of Tennessee; Aurelien Bouteiller, University of Tennessee; Amina Guermouche University of Tennessee; Thomas Herault, University of Tennessee; Yves Robert, ENS Lyon; Pierre Sens, LIP6 Paris; Jack Dongarra, University of Tennessee.
Building an infrastructure for exascale applications requires, in addition to many other key components, a stable and efficient failure detector. This paper describes the design and evaluation of a robust failure detector, able to maintain and distribute the correct list of alive resources within proven and scalable bounds.
The detection and distribution of the fault information follow different overlay topologies that together guarantee minimal disturbance to the applications. A virtual observation ring minimizes the overhead by allowing each node to be observed by another single node, providing an unobtrusive behavior.
The propagation stage is using a non-uniform variant of a reliable broadcast over a circulant graph overlay network, and guarantees a logarithmic fault propagation. Extensive simulations, together with experiments on the ORNL Titan supercomputer, show that the algorithm performs extremely well and exhibits all the desired properties of an exascale-ready algorithm.
Performance Modeling of In Situ Rendering, Matthew Larsen, University of Oregon; Cyrus Harrison, Lawrence Livermore National Laboratory; James Kress, University of Oregon; Dave Pugmire, Oak Ridge National Laboratory; Jeremy Meredith, Oak Ridge National Laboratory; Hank Childs, University of Oregon.
With the push to exascale, in situ visualization and analysis will continue to play an important role in HPC. Tightly coupling in situ visualization with simulations constrains resources for both, and these constraints force a complex balance of trade-offs. A performance model that provides an a priori answer for the cost of using an in situ approach for a given task would assist in managing the trade-offs between simulation and visualization resources.
In this work, we present new statistical performance models, based on algorithmic complexity, that accurately predict the run-time cost of a set of representative rendering algorithms, an essential in situ visualization task. To train and validate the models, we conduct a performance study of an MPI+X rendering infrastructure used in situ with three HPC simulation applications. We then explore feasibility issues using the model for selected in situ rendering questions.
An Efficient and Scalable Algorithmic Method for Generating Large-Scale Random Graphs, Maksudul Alam, Virginia Polytechnic Institute and State University; Maleq Khan, Virginia Polytechnic Institute and State University; Anil Vullikanti, Virginia Polytechnic Institute and State University; Madhav Marathe, Virginia Polytechnic Institute and State University.
Many real-world systems are modeled and analyzed using various random network models. For realistic analysis, models must incorporate relevant properties such as degree distribution and clustering coefficient. Many models, such as the Chung-Lu, stochastic Kronecker, stochastic blockmodels (SBM), and block two-level Erdos-Renyi (BTER) models have been devised to capture those properties.
However, the generative algorithms for these models are mostly sequential and take a prohibitively long time. In this paper, we present a novel time and space efficient algorithm for the Chung-Lu model requiring O(m) time and O(Λ) space, where m and Λ are the number of edges and distinct degrees.
We also present a distributed-memory parallel algorithm with P processors requiring O(m/P+Λ+P) time and O(Λ) space. Finally, we extend our algorithms for two other popular models: SBM and BTER. These algorithms are highly scalable. Generating a power-law network with 250 billion edges takes only 12 seconds using 1024 processors.
Daino: A High-Level Framework for Parallel and Efficient AMR on GPUs, Mohamed Wahib Attia, RIKEN; Naoya Maruyama, RIKEN; and Takayuki Aoki, Tokyo Institute of Technology.
Adaptive Mesh Refinement methods reduce computational requirements of problems by increasing resolution for only areas of interest. However, in practice, efficient AMR implementations are difficult considering that the mesh hierarchy management must be optimized for the underlying hardware. Architecture complexity of GPUs can render efficient AMR to be particularly challenging in GPU-accelerated supercomputers.
This paper presents a compiler-based high-level framework that can automatically transform serial uniform mesh code annotated by the user into parallel adaptive mesh code optimized for GPU-accelerated supercomputers. We also present a method for empirical analysis of a uniform mesh to project an upper-bound on achievable speedup of a GPU-optimized AMR code.
We show experimental results on three production applications. The speedup of code generated by our framework is comparable to hand-written AMR code while achieving good and weak scaling up to 1000 GPUs.