Sept. 22 — Research on new and emerging devices, circuits and architectures for computing, such as that pursued under the Nanoelectronics Research Initiative (NRI), can ultimately take high performance computing well beyond Exascale. Investing in exploratory research now can have a big impact beyond 2025. Invited speaker Dr. Thomas Theis is Executive Director of the Columbia Nano Initiative (CNI) and Professor in Electrical Engineering in the Fu Foundation School of Engineering, Arts and Sciences.

Full Abstract

The continuing evolution of silicon complementary metal–oxide–semiconductor (CMOS) technology is clearly approaching some important physical limits. Since roughly 2003, the inability to reduce supply voltages according to constant-electric-field scaling rules, combined with economic constraints on power density and total power, has forced designers to limit clock frequencies even as devices have continued to shrink. Still, there is a plausible path to Exascale, based on the continued evolution of silicon device technology, silicon photonics, 3D integration, and more.

The immediate challenge is to execute. However, longer term research exploring entirely new devices and architectures is essential if we want to take high performance computing well beyond Exascale. Recent years have brought a large increase in research funding and interest in new device concepts. Some of the devices explored to date, such as tunneling field-effect transistors (TFETs) based on III-V semiconductors, promise to open a new low-power design space which is inaccessible to conventional field-effect transistors (FETs).

Nanomagnetic devices may allow memory and logic functions to be combined in novel ways. And newer, perhaps more promising device concepts continue to emerge. At the same time, research in new architectures has also grown. Indeed, at the leading edge, researchers are beginning to focus on co-optimization of new devices and new architectures. Despite the growing research investment, the landscape of promising research opportunities outside the “FET devices and circuits box” is still largely unexplored.

About the Speaker:

Dr. Thomas Theis is Executive Director of CNI and Professor in Electrical Engineering in the Fu Foundation School of Engineering, Arts and Sciences. He received a B.S. degree in physics from Rensselaer Polytechnic Institute in 1972, and M.S. and Ph.D. degrees from Brown University in 1974 and 1978, respectively. A portion of his Ph.D. research was done at the Technical University of Munich, where he completed a postdoctoral year before joining IBM Research in December of 1978.

At the IBM Watson Research Center he made important contributions to the understanding of electronic conduction in wide band-gap insulators. In 1982 he became manager of a group studying growth and properties of III-V semiconductors and published extensively on III-V materials and devices. From 1984 through 2015 he held various senior management and executive positions with IBM. In 1993 he was named Senior Manager, Silicon Science and Technology, where he coordinated the transfer of copper interconnection technology from IBM Research to the IBM Microelectronics Division. The replacement of aluminum chip wiring by copper was an industry first, the biggest change in chip wiring technology in 30 years, and involved close collaboration between research, product development, and manufacturing organizations.

He served as IBM’s strategist for exploratory research worldwide from 1998 to 2012 and as Director, Physical Sciences from 1998 to 2010, conceiving and initiating successful research programs in silicon nanophotonics and Josephson junction-based quantum computing, and championing research in nanoelectronics, exploratory memory devices, and applications of information technology to address societal needs in energy, infrastructure, and the environment. From 2010 – 2012, as Program Manager, New Devices and Architectures for Computing, he organized new research projects aimed at greatly improved energy-efficiency in future computing systems.

In 2012, he went on assignment from IBM to the Semiconductor Research Corporation to lead SRC’s Nanoelectronics Research Initiative, a private-public partnership funding university research aimed at new devices and circuits for computing. He joined Columbia University in April of 2016 to manage and lead CNI operations and work with faculty and university research offices to identify and develop concepts for major new research programs. CNI’s shared research facilities provide critical support for Columbia’s research initiatives in Nanoscale Science and Engineering.

Dr. Theis is a Fellow of the IEEE, a Fellow of the American Physical Society, and the 2015 recipient of the George E. Pake Prize of the American Physical Society. He has served on numerous advisory boards and committees including the advisory board of the National Nanofabrication Infrastructure Network, the Board of Physics and Astronomy, the Physics Policy Committee of the APS, the Corporate Associates Advisory Board of the AIP, and the National Academies committees that authored the first and second triennial reviews of the U.S. National Nanotechnology Initiative and the report, “Physics 2010, Condensed Matter and Materials Physics”. He also served on the committee that authored the Report to the President and Congress on the Third Assessment of the National Nanotechnology Initiative for the President’s Council of Advisors on Science and Technology. He has authored or co-authored over 70 scientific and technical publications and is an inventor on four U.S. Patents.

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Source: SC16