Adolfy Hoisie
Chief Scientist for Computing & CENATE Director
PNNL

Adolfy Hoisie, a Pacific Northwest National Laboratory Fellow, serves as PNNL’s Chief Scientist for Computing. Before joining PNNL, he served in a variety of scientific and leadership positions at Los Alamos National Laboratory, including director of the Center for Advanced Architectures and Usable Supercomputing and leader of the Computer Science for High-Performance Computing Group and its Performance and Architecture Laboratory. Adolfy is an internationally recognized expert in performance analysis, modeling, and engineering of extreme-scale parallel computing systems and applications and system architecture. He has served as the principal investigator of projects with diverse funding sources, including the U.S. Department of Energy’s Office of Advanced Scientific Computing Research, National Nuclear Security Administration, Defense Advanced Research Projects Agency, National Science Foundation, and U.S. Department of Defense, among others. He has pioneered methods in his areas of expertise, creating practical, highly accurate performance modeling techniques that have set the standard in the community. Adolfy is a past winner of the Gordon Bell Award and has served extensively in the high-performance computing community in various capacities, including conference organizer, editorial board member, committee and panel member, and on advisory boards. He has published extensively in peer-reviewed literature and co-authored three books.

HPCwire: Hi Adolfy. Congratulations on being selected as an HPCwire 2017 Person to Watch. The Center for Advanced Technology Evaluation (CENATE) at PNNL has been up and running for more than a year now. What can you share with us about CENATE’s goals and what the challenges were in getting it up & running?

Adolfy Hoisie: CENATE is a nexus for evaluating technologies that are foundational for extreme-scale systems—all within a first-of-its-kind computing proving ground. Funded by the Department of Energy’s Office of Advanced Scientific Computing Research, CENATE’s mission is to deliver concrete benefits to further the performance and efficiency of DOE’s systems and applications to the computing technology arena and the computing research community.

The idea is straightforward: CENATE created a focal point for the evaluation of early systems technologies that too often are conducted between isolated research teams and technology providers. CENATE provides a much-needed research and development connection function. The intent is to productively impact the major advancements necessary for computing technology and energy efficiency in the transition to exascale and beyond.

The CENATE core encompasses testbed design and enablement, instrumentation, evaluation, and modeling and simulation research areas that primarily will focus on technologies aimed at improving the performance of applications of interest to DOE, both numerically and data-intensive, with the notion that the broader HPC community can take advantage of synergies as they develop.

Through its integrated approach to combining advanced concepts and technology, the CENATE measure–model–design pipeline remains unique among similar early analysis capability providers. CENATE tackles technologies at various stages in their maturity pipeline, all the way from early concepts that could materialize “beyond Moore’s law” to pre-production systems. Another dimension of the technology exploration is the spectrum of integration from disparate subsystems, such as a memory board, to a fully integrated system. Along this dimension, CENATE’s unique capabilities in modeling of simulation and design space exploration can be applied to analyzing advanced architectures that are expected to emerge from the union of diverse technologies.

CENATE facilities will be made available to the DOE laboratory community, and the findings will be disseminated among the DOE complex and to technology provider communities within non-disclosure and intellectual property limitations.

The challenges of standing up and running CENATE come from the “embarrassment of riches” effect. We are witnessing an unprecedented explosion in the diversity of architectural choices under fast-changing application workloads of interest in the DOE and computing community at large—with ubiquity of computing at all scales, from embedded to the extreme. Choices are multiple and must be weighted against the necessarily limited resource availability that applies to any research project. The CENATE team’s technology astuteness, augmented and guided by its Steering Committee and Technology Advisory boards, is crucial to enabling the promising technology within CENATE.

HPCwire: Looking at the technologies CENATE is now working on, which do you find most exciting and why?

We have assembled an exciting lineup of CENATE testbeds in the short time since the Center’s inception, which includes:

• ConTutto: A testing board designed by IBM to experiment with novel memory technologies within a working system. The first ConTutto deployment will exercise non-volatile Spin Torque Transfer magnetic memory (STT-MRAM) produced by Everspin.
• Data Vortex: High Probability Congestion Free Network. A novel networking design and technology from Data Vortex.
• DGX-1: GPU specialized for Machine Learning. The NVIDIA DGX-1 is the first system built with NVIDIA Pascal^™-powered Tesla^® P100 accelerators.
• HMC: Hybrid Memory Cube. Stacked memory from Micron.
• SEAPEARL: Power/Thermal Instrumented Cluster. The cluster consists of 52 nodes based on AMD and Intel CPUs, each instrumented with a mix of up to 21 power/temperature sensors that can collect measurements at runtime. Integrated by Penguin.

In addition, we are actively designing and procuring components for a new testbed, designed by CENATE, which features a combination of optical and electronic technology for the network. This new testbed is being done in collaboration with multiple vendors of computing technology, including networking and storage, and will allow for testing, evaluation, and design of new networking concepts.

The excitement within CENATE is not only related to the new technologies that we have in the machine room, but also to the wealth of opportunities that the various “knobs” given by the flexible design of the testbeds, allowing us to experiment with, analyze, design forward, and calibrate modeling and simulation. Moreover, we can “experiment ahead” through measurement (where available), modeling and simulation, and analysis with hybrid designs that could be unions of various technologies. For example, how would the contention properties of Data Vortex hold up if a hypothetical system fed the network at the bandwidth rates enabled by a stacked memory? CENATE affords this flexibility through the way testbeds are designed and, given the significant “bag-of-tools” it brings to bear in analysis, evaluation via modeling and simulation complemented by experiment, when practical.

HPCwire: What trends in high performance computing do you see as particularly relevant as you look forward to the year ahead?

When efficiency by various metrics is key, such as for exascale, increasing heterogeneity—and coping with it—is a mainstay concern. The ubiquity of machine learning as an application workload of choice and necessity at all scales of computing will lead to systems that do ML “natively,” including in the spirit of neuromorphic designs. A grand challenge, which we are tackling in CENATE along with many like-minded people in the community, relates to minimization of data movement as a key ingredient to power and performance optimization. The solution will not be confined to a single layer of the hardware-software stack. Hence, there’s a need for integrated approaches to technology evaluations for the applications and algorithms of interest, such as the one we are chartering in CENATE.

HPCwire: Outside of the professional sphere, what can you tell us about yourself – personal life, family, background, hobbies, etc.? Is there anything about you your colleagues might be surprised to learn?

I have a long-time love of flying mostly small airplanes. However, I don’t get to be a pilot much at all. Funny enough, I hate to travel, but I get to do it too much. Just as for architectures, not all flying is created equal.

Ian Buck NVIDIA	Adolfy Hoisie PNNL	John Martinis Google
Satoshi Matsuoka AIST AIRC	Paul Messina ECP	Bernd Mohr SC17
Andrew Ng Baidu	Kirk Skaugen Lenovo	Avinash Sodani Cavium
Lisa Su AMD	Jeffrey Vetter ORNL	Guangwen Yang NSCC Wuxi