The Ice Lake Top 10

By Trish Damkroger, Vice President and General Manager, High Performance Computing Group, Intel Corporation

November 16, 2020

New Intel® Xeon® Scalable processor-based servers are right around the corner. Code named “Ice Lake,” the upcoming 3rd Gen Xeon Scalable processors deliver significant performance and feature improvements for the HPC community. Here are 10 key highlights:

 

1) Sunny Cove Core Microarchitecture

Let’s start with the Sunny Cove core microarchitecture.  Ice Lake with Sunny Cove delivers an estimated 18% increase in instructions per clock (IPC) on integer and floating rate benchmarks1 at identical frequency, core count and memory bandwidth as the previous generation.  This new architecture is manufactured using Intel’s advanced 10nm process technology and includes increased L1 and L2 cache sizes as well as single thread execution enhancements. Ice Lake also includes new data security and platform integrity features such as Total Memory Encryption and support for Platform Firmware Resilience, in addition to new Intel Software Guard Extensions (see #5 below).

Be sure to catch Irma Esmer’s Tech Talk on “A Closer Look at Ice Lake” for details.

 

2) Increased Memory Channels

With a jump from six to eight DDR4 memory channels, Ice Lake improves Xeon’s baseline memory capacity and bandwidth to deliver a performance boost for memory-hungry workloads in industries like finance, manufacturing, and life sciences. Coupled with the Sunny Cove core’s architectural improvements, Ice Lake delivers an estimated 38% increase in performance on the SPEC floating point rate benchmark, at identical core count and frequency as the prior-generation server. 2

We’ll provide more performance data at Ice Lake launch in 2021.

 

3) Performance

While we won’t fully disclose Ice Lake’s full specifications and performance results until launch, we’re already seeing competitive advantage for several key benchmarks and applications.  At just half the cores, Ice Lake is expected to outperform 64-core AMD Rome systems for Monte Carlo, LAMMPS and NAMD3. Get additional details in my SC20 Executive Keynote video!

 

4) AVX-512

Intel AVX-512 instructions deliver double the flops per cycle versus AVX2. HPC users know this can significantly improve performance for applications in fields like molecular dynamics, options pricing, computational fluid dynamics and crash simulation. With Ice Lake’s boost in instructions per clock, this feature has even greater impact.

 

5) Speed Select Technology

Intel Speed Select Technology (SST) is like getting 3 processors in one. Users can specify up to three core/frequency/power configurations to help optimize performance per watt for the application being run. So you can adjust core counts and frequencies to match the needs of each workload. Intel SST also gives the hardware control over CPU frequency to allow continuous, precise matching of the power consumption to the workload’s needs.

 

6) Intel SGX

Intel’s Software Guard Extensions (SGX) provides a critical defense layer, giving applications a hardened enclave in memory for sensitive data and application code. This trusted execution environment can help to provide an extra level of data security and code integrity, particularly useful when sharing sensitive or proprietary data in multi-party federated analytics, modeling and simulation.

 

7) Intel Deep Learning Boost

Intel Xeon Scalable processors are the only mainstream server CPUs with built-in AI acceleration. Intel Deep Learning Boost in Ice Lake makes converged HPC and AI workloads much more efficient, with specialized instructions for codes benefiting from reduced or mixed precision numerics. In just one example from current generation Intel Xeni , we saw up to 9x better performance than competition for inference performance4.

 

8) Intel Optane Persistent Memory 200 Series

Support for Intel® Optane™ persistent memory 200 series provides larger memory pools and persistence—a game changer for data-intensive workloads from exascale storage to financial modeling. The 200 series delivers on average 25% more memory bandwidth than the previous generation and total per socket memory of 6 terabytes when combining DRAM and persistent memory.

 

9) PCIe Gen 4

With Ice Lake, Xeon Scalable processors now support PCIe Gen 4, doubling the I/O bandwidth performance compared to Gen 3. PCIe Gen 4 speeds data movement for FPGA and GPU accelerators that power machine and deep learning applications. It offers lower latency and higher bandwidth for next-generation Ethernet and NVMe storage.

 

10) Customers

And finally, what we love most about Ice Lake is how it will help our users and partners do great things, from climate science to the cloud.

We just announced this week that the Korean Meteorological Association (KMA) will be adopting Ice Lake for its Supercomputer No. 5 in January.  This system will be eight times faster than KMA’s current supercomputer, essential for the services KMA delivers, including weather prediction, climate change assessment, and earthquake and marine studies.

In addition, over the past week, Osaka University, the University of Tokyo, and the National Institute of Advanced Industrial Science and Technology (AIST) have all announced their choice of Ice Lake for upcoming systems.

Max Planck Computing and Data Facility has also chosen Ice Lake for their new Raven system, enabling groundbreaking research in physics, bioscience, theoretical chemistry and beyond.

We were also happy to see Oracle Cloud Infrastructure adopting Ice Lake to power HPC instances – you can read more about that here.

Stay tuned for more Ice Lake customer news as we get closer to launch in 2021.

 



1- GEOMEAN based on SIR and at the same core count, frequency and memory bandwidth when comparing to prior generation. Other workload IPC measurements may vary.  Per core results have been estimated based on pre-production tests at identical frequency and memory bandwidth per core as of October 2020.

2- GEOMEAN based on SIR and at the same core count and frequency when comparing to prior generation. Other workload IPC measurements may vary.  Per core results have been estimated based on pre-production tests as of Sept 2020.

3- NAMD STMV (1.2x performance advantage): 2S 3rd Gen Intel Xeon Scalable processor (Ice Lake): 1-node, 2x pre-production 3rd Gen Intel Xeon Scalable processor (Ice Lake – 2.2GHz, 32cores per socket), Intel reference platform, 256GB, 16x16GB 3200MHz DDR4, HT=on, TURBO=on, SNC=disabled, SSDSC2KG96 960GB, BIOS SE5C6200.86B.0017.D92.2007150417, microcode 0x8c000140, CentOS Linux 7.8, 3.10.0-1127.18.2.el7.crt1.x86_64, compiled with Intel C Compiler 2020u2, Intel MKL, NAMD: 2_15-Alpha1, tested by Intel on 9-17-2020.  2S AMD EPYC 7742: 1-node 2x AMD EPYC 7742 (2.25GHz, 64cores per socket), Supermicro platform, 16x16GB 3200MHz DDR4, SMT on, Boost on, NPS=4, SSDSC2KG96 960GB, BIOS2.0b dt 11/15/2019, microcode 0x8301025, CentOS Linux 7.7.1908, 3.10.0-1127.13.1.el7.crt1.x86_64, compiled with AOCC 2.2, Intel MKL, NAMD: 2_15-Alpha1, tested by Intel on 9-10-2020. Monte Carlo (1.3x performance advantage): 2S 3rd Gen  Intel Xeon Scalable processor (Ice Lake): 1-node, 2x pre-production 3rd Gen Intel Xeon Scalable processor (Ice Lake – 2.2GHz, 32cores per socket), Intel reference platform, 256GB, 16x16GB 3200MHz DDR4, HT=on, TURBO=on, SNC=disabled, SSDSC2KG96 960GB, BIOS SE5C6200.86B.0017.D92.2007150417, microcode 0x8c000140, CentOS Linux 7.8, 3.10.0-1127.18.2.el7.crt1.x86_64, compiled with Intel C Compiler 2020u2, Intel MKL 2020u2, Monte Carlo FSI Kernel workload developed by Intel, tested by Intel on 10-9-2020. 2S AMD EPYC 7742: 1-node 2x AMD EPYC 7742 (2.25GHz, 64cores per socket), Supermicro platform, 16x16GB 3200MHz DDR4, SMT on, Boost on, NPS=4, SSDSC2KG96 960GB, BIOS2.0b dt 11/15/2019, microcode 0x8301025, CentOS Linux 7.7.1908, 3.10.0-1127.13.1.el7.crt1.x86_64, compiled with Intel C Compiler 2020u2, Intel MKL 2020u2, Monte Carlo FSI Kernel workload developed by Intel, tested by Intel on 7-17-2020. LAMMPS (Geomean of Atomic Fluid, Copper, Liquid Crystal, Polyethylene, Protein, Stillinger-Weber, Tersoff, and Water) (1.2x performance advantage): 2S 3rd Gen  Intel Xeon Scalable processor (Ice Lake): 1-node, 2x pre-production 3rd Gen Intel Xeon Scalable processor (Ice Lake – 2.2GHz, 32cores per socket), Intel reference platform, 256GB, 16x16GB 3200MHz DDR4, HT=on, TURBO=on, SNC=disabled, SSDSC2KG96 960GB, BIOS SE5C6200.86B.0017.D92.2007150417, microcode 0x8c000140, CentOS Linux 7.8, 3.10.0-1127.18.2.el7.crt1.x86_64, compiled with Intel C Compiler 2020u2, Intel MKL 2020u2, LAMMPS 03/03/2020, tested by Intel on 10-9-20202S AMD EPYC 7742: 1-node 2x AMD EPYC 7742 (2.25GHz, 64cores per socket), Supermicro platform, 16x16GB 3200MHz DDR4, SMT on, Boost on, NPS=4, SSDSC2KG96 960GB, BIOS2.0b dt 11/15/2019, microcode 0x8301025, CentOS Linux 7.7.1908, 3.10.0-1127.13.1.el7.crt1.x86_64, compiled with AOCC 2.2, LAMMPS 07/21/2020, tested by Intel on 8-19-2020.

4- 9x AI: With Intel Xeon processor’s built-in workload acceleration tapping Intel Deep Learning Boost and AVX 512 technology, we are seeing advantages of up to 9x AI inference performance vs. competitor CPUs.. AI Inference: 9X performance achieved on MobileNet v1 on PyTorch framework on Xeon AP processor  (Xeon 9282)  Int 8 vs. competitor CPU (AMD 7742). Tested by Intel as of 11/13/2019. 2 socket Intel® Xeon® Platinum 9282 processors (56C), HT ON, Turbo ON, Total Memory 384 GB (24 slots, 16GB, 2934Mhz), BIOS: SE5C620.86B.2X.01.0053.081920190637, Microcode: 0x500002c, Ubuntu 19.10, Kernel 5.3.0-22-generic, SSD 1x Micron_5100_MTFDDAV480TBY 447G, Intel® Deep Learning Framework: PyTorch (master + PR for MLPerf)*git fetch origin pull/25235/head:mlperf; git checkout mlperf, Compiler GCC 9.2.1.20191008, MobileNetV1, Batch Size=64, Iterations: 1000, Datatype: INT8 vs Baseline: AMD EPYC™ 7742 processor configuration: Tested by Intel as of 11/13/2019. 2-socket AMD EPYC™ 7742 “Rome” processors (64C), HT ON, Turbo ON, Total Memory 512 GB (16 slots, 32GB, 3200Mhz), BIOS: 2.0, Microcode 0x830101C, Ubuntu 19.10, Kernel 5.3.0-22-generic, SSD 1x Intel® SSD D3-S4610 1.8T, Deep Learning Framework: PyTorch (master + PR for MLPerf) *git fetch origin pull/25235/head:mlperf; git checkout mlperf, GCC 9.2.1.20191008, MobileNetV1, Batch Size=64, Iterations: 1000, Datatype: FP32. See https://www.intel.com/content/www/us/en/benchmarks/2019-xeon-scalable-benchmark.html claim 33


All product plans and roadmaps are subject to change without notice.

Intel technologies may require enabled hardware, software or service activation.

Performance result estimates are as of dates shown in configurations and may not reflect all publicly available updates.  No product or component can be absolutely secure.

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex​.

Intel Advanced Vector Extensions (Intel AVX) provides higher throughput to certain processor operations. Due to varying processor power characteristics, utilizing AVX instructions may cause a) some parts to operate at less than the rated frequency and b) some parts with Intel Turbo Boost Technology 2.0 to not achieve any or maximum turbo frequencies. Performance varies depending on hardware, software, and system configuration and you can learn more at http://www.intel.com/go/turbo.

Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not “commercial” names and not intended to function as trademarks.

Results have been estimated or simulated.

Your costs and results may vary.

Intel does not control or audit third-party data.  You should consult other sources to evaluate accuracy.

© Intel Corporation . Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

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