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Semiconductor Companies Create Building Block for Chiplet Design
January 24, 2023
Intel's CEO Pat Gelsinger last week made a grand proclamation that chips will be for the next few decades what oil and gas was to the world over the last 50 years. While that remains to be seen, two technology associations are joining hands to develop building blocks to stabilize the development of future chip designs. The goal of the standard is to set the stage for a thriving marketplace that fuels... Read more…
AMD’s Genoa CPUs Offer Up to 96 5nm Cores Across 12 Chiplets
November 10, 2022
AMD’s fourth-generation Epyc processor line has arrived, starting with the “general-purpose” architecture, called “Genoa,” the successor to third-gen Eypc Milan, which debuted in March of last year. At a launch event held today in San Francisco, AMD announced the general availability of the latest Epyc CPUs with up to 96 TSMC 5nm Zen 4 cores... Read more…
Intel’s New Programmable Chips Next Year to Replace Aging Products
September 27, 2022
Intel shared its latest roadmap of programmable chips, and doesn't want to dig itself into a hole by following AMD's strategy in the area. "We're thankfully not matching their strategy," said Shannon Poulin, corporate vice president for the datacenter and AI group at Intel, in response to a question posed by HPCwire during a press briefing. The updated roadmap pieces together Intel's strategy for FPGAs... Read more…
Intel Says UCIe to Outpace PCIe in Speed Race
May 11, 2022
Intel has shared more details on a new interconnect that is the foundation of the company’s long-term plan for x86, Arm and RISC-V architectures to co-exist in a single chip package. The semiconductor company is taking a modular approach to chip design with the option for customers to cram computing blocks such as CPUs, GPUs and AI accelerators inside a single chip package. Read more…
AMD Milan-X CPU with 3D V-Cache Available in Four SKUs, Up to 64-Cores
March 21, 2022
Following their debut launch in November, AMD Epyc processors with 3D V-Cache technology, codenamed Milan-X, are now generally available from major system-makers as well as from cloud provider Microsoft Azure. Available in four SKUs and ranging from 16- to 64-cores, the new processors feature 768 megabytes of L3 cache... Read more…
Industry Consortium Forms to Drive UCIe Chiplet Interconnect Standard
March 2, 2022
A new industry consortium aims to establish a die-to-die interconnect standard – Universal Chiplet Interconnect Express (UCIe) – in support of an open chipl Read more…
AMD Launches Milan-X CPU with 3D V-Cache and Multichip Instinct MI200 GPU
November 8, 2021
At a virtual event this morning, AMD CEO Lisa Su unveiled the company’s latest and much-anticipated server products: the new Milan-X CPU, which leverages AMD’s new 3D V-Cache technology; and its new Instinct MI200 GPU, which provides up to 220 compute units across two Infinity Fabric-connected dies, delivering an astounding 47.9 peak double-precision teraflops. “We're in a high-performance... Read more…
UCLA Researchers Report Largest Chiplet Design and Early Prototyping
October 12, 2021
What’s the best path forward for large-scale chip/system integration? Good question. Cerebras has set a high bar with its wafer scale engine 2 (WSE-2); it has 2.6 trillion transistors, including 850,000 cores, and was fabricated using TSMC’s 7nm process on a roughly 8” x 8” silicon footprint. Read more…
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Whitepaper
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Whitepaper
Porting CUDA Applications to Run on AMD GPUs
A workload-driven system capable of running HPC/AI workloads is more important than ever. Organizations face many challenges when building a system capable of running HPC and AI workloads. There are also many complexities in system design and integration. Building a workload driven solution requires expertise and domain knowledge that organizational staff may not possess.
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