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MEMCON 2024: Insights into CXL, HBM, GenAI, and More
March 6, 2024
As the world focuses on GenAI, there is still plenty of other computing going on worldwide. A common denominator is the expanding role of memory technology in G Read more…
Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU
December 14, 2023
As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…
The Divergent Evolution of the Next Generation Xeon Processor
September 7, 2023
At the recent Hot Chips meeting, Intel revealed technical specifications and features for the next-generation Xeon architecture arriving in 2024. While the next Read more…
GigaIO’s New SuperNODE Takes-off with Record Breaking AMD GPU Performance
August 10, 2023
The HPC users dream is to keep stuffing GPUs into a rack mount box and make everything go faster. Some servers offer up to eight GPUs, but the standard server u Read more…
RISC-V Moving Toward Open Server Specification
July 24, 2023
A specification that could standardize the development of RISC-V server chips and systems is currently being drafted by RISC-V International, an organization th Read more…
Intel Admits GPU Mistakes, Reveals New Supercomputing Chip Roadmap
May 22, 2023
Intel has finally provided specific details on wholesale changes it has made to its supercomputing chip roadmap after an abrupt reversal of an ambitious plan to Read more…
CXL Brings Datacenter-sized Computing with 3.0 Standard, Thinks Ahead to 4.0
August 2, 2022
A new version of a standard backed by major cloud providers and chip companies could change the way some of the world's largest datacenters and fastest supercomputers are built. The CXL Consortium on Tuesday announced a new specification called CXL 3.0 – also known as Compute Express Link 3.0... Read more…
UCIe Consortium Incorporates, Nvidia and Alibaba Round Out Board
August 2, 2022
The Universal Chiplet Interconnect Express (UCIe) consortium is moving ahead with its effort to standardize a universal interconnect at the package level. The c Read more…
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