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Tag: intel phi

Getting ready for KNL? Take a Lesson from NERSC on Optimizing

Feb 10, 2016 |

NERSC is beginning to tell the world how to optimize applications to run on the new Intel Xeon Phi processors, code name Knights Landing (KNL), that will boot in self-hosted mode to power over 9,300 nodes of the Cori supercomputer by the summer of 2016. Indeed, general availability of KNL is expected before the end Read more…

Contrary View: CPUs Sometimes Best for Big Data Visualization

Dec 1, 2015 |

Contrary to conventional thinking, GPUs are often not the best vehicles for big data visualization. In this commentary, I discuss several key technical reasons why a CPU-based “Software Defined Visualization” approach can deliver a more flexible, performant, scalable, cost effective, and power efficient solution to big data visualization than a conventional GPU-based approach. An example Read more…

Speaking Many Languages into the MIC

May 8, 2013 |

Traditional HPC languages, Fortran, C and C++, have little native control over hardware capabilities such as SIMD operations, multi-core availability and prefetch instructions. The burden of optimization is therefore…

Heterogeneous Computing in Firing Range

Apr 8, 2013 |

Despite developer hassle, this is a great problem from the perspective of companies who are finding ways to tailor clean layers around complex code for heterogeneous computing. Take, for example, Atlanta-based AccelerEyes, which is seeing booming business because of the demand for GPU acceleration and interest in kicking the Xeon Phi co-processor tires.