Tom Tabor, publisher of HPCwire and HPC in the Cloud, gives his perspective on SC’10, which just celebrated its 25th year with the biggest turnout yet.
Last week, the InfiniBand Trade Association (IBTA) used the International Supercomputing Conference (ISC’10) to unveil the new roadmap for InfiniBand. In a nutshell, the IBTA is moving the technology to 104 Gbps, using a new coding scheme that promises 100 Gbps of useful data in a 4-lane configuration.
Addison and Michael are joined by Nicole Hemsoth, editor of HPC in the Cloud, to offer their impressions of ISC’10.
The petascale era of supercomputing is barely underway, but the effort to reach the exascale level has already begun. The University of Tennessee’s Jack Dongarra has been involved with an international project to develop software that will support exascale computing. We got a chance to speak with him before ISC and talk about the work being done.
Returning to ISC after a hiatus of several years and viewing the event from the vantage point of an industry analyst, the show appears to have made a quantum leap in terms of size and sophistication of the exhibit, and degree and intensity of business activity.
University of Tennessee’s Jack Dongarra, NCSA’s Thom Dunning, and Stuttgart HPC Chief Michael Resch share some thoughts on day 3 of ISC.
Even as we gain a footing in the era of petaflops computing, we have set in motion the exploration of the undiscovered domain of exaflops computing. This year has seen the launching of multiple programs to develop the concepts, architectures, software stack, programming models, and new families of parallel algorithms necessary to enable the practical realization of exaflops capability prior to the end of this decade.
Berkeley Lab’s John Shalf and LSU’s Thomas Sterling give a rundown on some of the events that took place the first day of the conference.
Heike Jagode, of the University of Tennessee, takes us through some of the exhibits and sessions on day 2 of the conference.
Chipmaker Intel is reviving the Larrabee technology for the HPC market, with plans to bring a manycore coprocessor to market in the next few years. During the ISC’10 opening keynote, Kirk Skaugen, vice president of Intel’s Architecture Group and general manager of the Data Center Group, announced the chipmaker is developing what they’re calling a “Many Integrated Core” (MIC) architecture, which will be the basis of a new line of processors aimed squarely at high performance technical computing applications.