Tag: memory wall
Ahead of his opening conference keynote at ISC’13, Bill Dally, chief scientist at NVIDIA and senior vice president of NVIDIA Research, shares his views on where HPC is headed. Among the key topics covered are the demand for heterogenous computing, overcoming the memory wall, the implications of government belt-tightening, and much more…
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HMC_side_view_SC12_small.jpg” alt=”” width=”95″ height=”85″ />The next-generation memory-maker Micron Technology was one of the many innovative companies demonstrating its wares on the Supercomputing Conference (SC12) show floor last November. Micron’s General Manager of Hybrid Technology Scott Graham was on hand to discuss the latest developments in their Hybrid Memory Cube (HMC) technology, a multi-chip module that aims to address one of the biggest challenges in high performance computing: scaling the memory wall.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HMC_transparent.bmp” alt=”” width=”117″ height=”91″ />Computer memory is currently undergoing something of an identity crisis. For the past 8 years, multicore microprocessors have been creating a performance discontinuity, the so-called memory wall. It’s now fairly clear that this widening gap between compute and memory performance will not be solved with conventional DRAM products. But there is one technology under development that aims to close that gap, and its first use case will likely be in the ethereal realm of supercomputing.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/HP_Corona_graphic.bmp” alt=”” width=”109″ height=”95″ />In high performance computing, Hewlett-Packard is best known for supplying bread-and-butter HPC systems, built with standard processors and interconnects. But the company’s research arm has been devising a manycore chipset, which would outrun the average-sized HPC cluster of today. The design represents a radical leap in performance, and if implemented, would fulfill the promise of exascale computing.
Additional performance increases for supercomputers are being confounded by three walls: the power wall, the memory wall and the datacenter wall (the “wall wall”). To overcome these hurdles, the market is currently looking to a combination of four strategies: parallel applications development, adding accelerators to standard commodity compute nodes, developing new purpose-built systems, and waiting for a technology breakthrough.
It is a common belief that only sequential applications need to be adapted for parallel execution on multicore processors. However, many existing parallel algorithms are also a poor fit. They have simply been optimized for the wrong design parameters.
As cores proliferate on CPUs, the memory wall rises higher and applications have an increasingly difficult task of using processor resources efficiently. But hardware alone is not to blame. Making the software more efficient may be the simplest and least expensive way to save power and resources on modern multicore architectures.
The new Nehalem processors will push the memory wall back a bit…at least for a while.
Nevermind the cores. Just hand over the cache.
Solving the “memory wall” problem is going to be key to unleasing the performance of manycore microprocessors.