Optimizing Codes for Heterogeneous HPC Clusters Using OpenACC

July 3, 2017

Looking at the Top500 and Green500 ranks, one clearly realizes that most HPC systems are heterogeneous architecture using COTS (Commercial Off-The-Shelf) hardware, combining traditional multi-core CPUs with massively parallel accelerators, such as GPUs and MICs. With processor frequencies now hitting a solid wall, the only truly open avenue for riding today the Moore’s law is increasing hardware parallelism in several different ways: more computing nodes, more processors in each node, more cores within each processor, and longer vector instructions in each core. Read more…

By Enrico Calore et. al.

Code Modernization: Bringing Codes Into the Parallel Age

June 8, 2017

The ways that advanced computing performance depends on more – much more – than the processor take many forms. Regardless of Moore’s Law validity, it’s Read more…

By Doug Black

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn't made the task of parallel progr Read more…

By Tiffany Trader

MIT’s Multicore Swarm Architecture Advances Ordered Parallelism

July 21, 2016

A relatively new architecture explicitly designed for parallelism – Swarm – based on work at MIT has shown promise for substantially speeding up classes of Read more…

By John Russell

James Reinders: Parallelism Has Crossed a Threshold

February 4, 2016

Is the parallel everything era here? What happens when you can assume parallel cores? In the second half of our in-depth interview, Intel's James Reinders discu Read more…

By Tiffany Trader

A Conversation with James Reinders

January 21, 2016

As Chief Evangelist of Intel Software Products, James Reinders spends most of his working hours thinking about and promoting parallel programming. He’s ess Read more…

By Tiffany Trader and John Russell

Intel Haswell-EX Server Sets STAC-A2 Performance Record

September 2, 2015

Intel has reasserted its prominence on a subset of financial benchmarks designed to evaluate platforms for the pricing and market risk analytics. More powerful Read more…

By Tiffany Trader

COSMOS Team Achieves 100x Speedup on Cosmology Code

August 24, 2015

One of the most popular sessions at the Intel Developer Forum last week in San Francisco, and certainly one of the most exciting from an HPC perspective, broug Read more…

By Tiffany Trader

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Full & Complete coverage of SC17

Keynote Reviews, Analysts Write Ups, Booth Vidoes, Student Competition, Awards and so much

Did you miss out on Supercomputing 2017? Did you attend, but were stuck in meetings the whole time without an opportunity to walk the show floor and see what new announcements were being made? HPCwire's got you covered, we visited some of the hottest booths in the exhibit hall and spoke with their top executives to get the scoop on the latest solutions, partnerships, and product announcements.

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Avoiding the Storage Silo Trap; Best Practices for Data Storage in Scientific Research

From mismatches between compute and storage capabilities to colossal data volumes, data storage presents a number of challenges for scientific research. And as silos pop up and challenges expand, the pace of research often suffers.

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Creating a Modular, Building-Block Architecture for Life Science Workflows

As genomic data becomes ubiquitous, infrastructure bottlenecks for life sciences organizations are narrowing. But speedy analysis and real-time decision making don't have to remain out of reach: modern end-to-end systems are emerging as flexible solutions for a competitive edge.

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