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]]>MIT spin-out Lyric Semiconductor Inc. has launched a new breed of integrated circuits that replaces the binary logic of traditional computing with probabilistic logic. The aim is to deliver a much more efficient architecture for applications based on probability computing. For these types of workloads, the company is promising orders-of-magnitude improvement in energy efficiency, performance and cost.

Essentially, what Lyric has come up with is a fifth processor architecture, following CPUs, GPUs, DSPs, and FPGAs. The technology grew out of Ben Vigoda’s Ph.D. thesis work at MIT more than 10 years ago. In 2006, Vigoda founded the company, along with IC designer David Reynolds and Analog Devices CEO Ray Stata. Vigoda became the CEO, Reynolds the VP of product development, and Stata took the post of chairman of Lyric’s board (with Stata Venture Partners listed as the lead investor). The company has filed 50 patents to protect its intellectual property and raised over $20 million to get the business off the ground. About $18 million of that funding was injected from DARPA and other government agencies to spur the research and development effort and make probability processing a viable technology.

The goal is to construct hardware circuitry and software purpose-built for probability applications. With conventional digital technology, processing has to follow a strictly linear path. This is fine for software like operating systems, spreadsheets, word processing, and database transactions, where the computing consists of straightforward calculations or data movement. “But most of the interesting things happening nowadays don’t really fit into that model,” says Reynolds. From his perspective, the goal of more and more software today is to find the best fit or most likely answer (or answers) to a problem.

Most data mining, predictive analytics, pattern recognition, and modeling/simulation codes fall into this category. That encompasses a wide range of applications including Web searching, financial modeling, genome sequence analysis, speech recognition, climate modeling, credit fraud detection, spam filtering, and financial modeling, among many others. People tend to associate these probability-based applications with human-like intelligence, and this is clearly where software, in general, is moving.

Even today, the average person uses probability computing on a fairly regular basis. For example, when you hop onto Amazon’s website, the software behind the scenes attempts to predict what product you might be interested in buying, basing its suggestions on past shopping behavior and what you’re currently clicking on. If you do make a purchase, the credit card company’s software tries to determine if the charge is fraudulent or not, again based on past buying habits. Both of these pieces of software are searching for the most likely result, rather than a specific answer. “So these applications are not a great fit for the traditional digital processor as we know it,” says Reynolds.

Probability computing has been around for decades, but most of the work has involved developing languages and algorithms, which are subsequently applied to vanilla digital computers. Lyric’s founders were convinced that they needed to rethink the design of the underlying circuitry to get the optimal solution. What they came up with was the concept of pbits (probability bits), which unlike Boolean bits can represent a lot more than two states. Lyric is not divulging exactly how many states that might be, but according to Reynolds: “Suffice to say that we have all the states we need for the applications we’ve looked at so far.”

To process pbits, Lyric has designed a set of standard probability logic gates that can be connected to one another multi-directionally. So instead of stepping through an application in a linear sequence using Boolean gates, more complex operations, such as getting the intersection of data, can be performed on multiple variables in parallel. That, says Reynolds, is a much more natural way of implementing parallelism than CPUs provide with multicore and multi-threading architectures.

According to him, for probabilistic-type operations, what took 500 transistors with conventional digital logic can be distilled down to just a handful of probability transistors. Lyric predicts that a single probability processor will be able to increase computational capability by two or three orders of magnitude compared to today’s server chips, with commensurate savings in cost, power and space.

The company’s first commercial product will be aimed at advanced error correction for NAND flash memory. Called Lyric Error Correction (LEC), it’s designed to relieve the flash memory ECC bottleneck, which is becoming a constraint as semiconductor process geometries shrink. On the 30nm process, flash memory errors are generated at the rate of 1 in 1,000. On the next generation technology, it will be 1 in 100. That means the ECC component of the controller, which is already the largest piece of the device, may become impractical to implement.

As it turns out advanced ECC logic is based on probabilities, so it’s a nice fit for Lyric-style circuits. The company is promising a 30-fold reduction in die real estate (for 1 Gbps bandwidths) and a 12-fold improvement in power. The company has ported the device to different process nodes using TSMC as the fab partner, and is claiming yields typical for this class of application. LEC is available for licensing today, with product integration expected in 12 months.

But the real payoff for Lyric is at least a few years down the road. The company is developing the GP5, which stands for general-purpose programmable probability processing platform. The technology is aimed at the broader set of probability applications mentioned above, and, according to the company, will be up to 1,000 times more efficient at these types of tasks than current x86 CPUs. The first samples of the GP5 are slated to appear in 2013.

According to Mira Wilczek, Lyric’s director of business development, the initial commercial implementations of the GP5 are likely to be packaged inside an appliance or embedded device, such as a Web search server or a handheld speech recognition device. A more general-purpose use case could involve a GP5 used as a coprocessor in conjunction with a CPU.

For high performance computing work, the latter configuration could be a way to accelerate performance on applications such as materials modeling and whole genome analysis, in much the same way as GPGPUs are being employed today. “Just like a GPU exploits the vector nature of graphics computation, we exploit the typical structures that our algorithms take for probability computation,” explains Wilczek.

The downside to the new architecture is that conventional programming languages, like C, Fortran and Java, are not very good at expressing probability algorithms. Lyric has come up with its own language, called PSBL (Probability Synthesizes to Bayesian Logic) that can be compiled to their hardware. The language is a rule-based language, where the programmer specifies the constraints of the problems, rather than how to solve it. Other probability-type programming languages, like R and the Microsoft’s Infer.NET could also presumably be targeted to Lyric’s architecture.

PSBL 1.0 will be licensed to select partners in Q4 2010 with a second version slated for Q4 2010. In the absence of Lyric hardware, the PSBL code can be compiled to run in a simulator on a conventional computer, albeit much more slowly. When the GP5 arrives in 2013, the hope is to have the foundation of a probability computing ecosystem already in place.

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