Tag: processor
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/TI_ARM_DSP_SoC_small.bmp” alt=”” width=”90″ height=”94″ />NVIDIA, Intel and AMD were not the only chip vendors unveiling new HPC accelerators last week SC12. Texas Instruments (TI) announced a set of heterogeneous processors that they believe will offer among the best performance per watt in the industry. In this case, the chipmaker glued an ARM CPU and DSP together on the same die, offering a low-power SoC with an impressive number of FLOPS.
Chipmaker unveils Opteron 6300 series — same core count, more performance.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Epiphany_16_small.JPG” alt=”” width=”93″ height=”79″ />Chipmaker Adapteva is attempting to bypass the conventional venture capital funding route and collect money via a micro-investor platform known as Kickstarter. In the process, the company will open up its software and hardware design for its manycore Epiphany architecture, and deliver a parallel computing kit to anyone who can ante up $99.
Chip manufacturer plans to offer 14nm FinFET transistors in 2014.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/computer_chips_on_die_small.jpg” alt=”” width=”94″ height=”85″ />Intel has begun to formulate a strategy that will integrate fabric controllers with its server processors. According to Raj Hazra, general manager of the Technical Computing unit at Intel, the company is planning to use the recently acquired IP from Cray, QLogic and Fulcrum to deliver chips that put what is essentially a NIC onto the processor die. In a recent conversation with Hazra, he outlined their new fabric interconnect strategy.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/circuits.jpg” alt=”” width=”112″ height=”101″ />In a recent report in Real World Technologies, chip guru David Kanter dissects the new 64-bit ARM design and what it might mean to the IT landscape. His take on the architecture is almost uniformly positive, noting that not only did the designers manage to develop an elegant instruction set that was backwardly compatible with the existing ISA, but they also took the extra step to jettison a few of the poorly designed features of the 32-bit architecture.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg” alt=”” width=”99″ height=”78″ />Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Opteron_processor_small.png” alt=”” width=”99″ height=”74″ />AMD has announced an update to their Opteron 6200 family aimed at HPC and performance-driven enterprise applications. The new 16-core Opteron 6278 and 6284 SE processors fall under the Bulldozer architecture, sporting similar core density and cache as their predecessors.
<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Intel-Corp_small.jpg” alt=”” width=”90″ height=”65″ />Intel Corp. has launched three new families of Xeon processors, joining the Xeon E5-2600 series the chipmaker introduced in March. These latest chips span the entire market for the Xeon line, from four- and two-socket servers, down to entry-level workstations and microservers. A number of HPC server makers, including SGI, Dell, and Appro announced updated hardware based on the new silicon.
Featured Events
-
LinuxCon + ContainerCon Europe 2016
October 4 - October 6Berlin Germany -
AI World
November 7 - November 9San Francisco CA United States -
SC16
November 13 - November 17Salt Lake City UT United States -
ISC 2017
June 18, 2017 - June 22, 2017Frankfurt Hessen Germany