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The Department of Energy (DOE) plans to invest $16 million over the next four years in supercomputer technology that will accelerate the design of new materials by combining “theoretical and experimental efforts to create new validated codes.” The new program will focus on software development that eventually may run on exascale machines. Luke Shulenburger of Sandia Read more…
Declining DNA sequencing costs and the rush to do whole genome sequencing (WGS) of large cohort populations – think 5000 subjects now, but many more thousands soon – presents a formidable computational challenge to researchers attempting to make sense of large cohort datasets. No single architecture is best. This month researchers report developing a hybrid Read more…
Throughout the past year, the National Center for Supercomputing Applications has been celebrating its 30th anniversary. On Friday, Larry Smarr, whose unsolicited 1983 proposal to the National Science Foundation (NSF) begat NCSA in 1985 and helped spur NSF to create not one but five national centers for supercomputing, gave a celebratory talk at NCSA.
Not long after revealing more details about its next-gen Power9 chip due in 2017, IBM today rolled out three new Power8-based Linux servers and a new version of its Power8 chip featuring on-chip NVLink interconnect. One of the servers – Power S822LC for High Performance Computing – uses the new chip (Power8 with NVLink) to Read more…
The three-year European SAVE project, which wraps up this week, has produced tools and technologies that can help reduce heterogeneous system architecture (HSA) energy costs by 20 percent say its organizers. SAVE is the somewhat abbreviated acronym for Self-Adaptive Virtualization-Aware High-Performance/Low-Energy Heterogeneous System Architectures, a EU collaborative research project, funded by the EU’s Seventh Framework Read more…
China’s impressive standing up of the 93 petaflops Sunway TaihuLight atop the Top500 list in June ruffled more than a few feathers in the west. Here’s yet more fodder for stirring up geo-computational acumen nervousness – a report by HackerRank, a blog that posts coding challenges, indicates the U.S. would place 28th in a Coding Olympics Read more…
Sorting out computational biology’s future is tricky. It likely won’t be singular. First-principle, mechanistic simulation has so far proven challenging but could eventually become game changing. Meanwhile pattern recognition and matching in massive ‘omics’ datasets have been extremely productive and likely to remain dominant at present. Now, an MIT professor and colleagues write that two Read more…
ARM and Fujitsu today announced a scalable vector extension (SVE) to the ARMv8-A architecture intended to enhance ARM capabilities in HPC workloads. Fujitsu is the lead silicon partner in the effort (so far) and will use ARM with SVE technology in its post K computer, Japan’s next flagship supercomputer planned for the 2020 timeframe. This is an important incremental step for ARM, which seeks to push more aggressively into mainstream and HPC server markets.
With early adopters of application container technology completing early testing in multi-tenant settings, potential performance issues are beginning to surface. Among them, according to hyper-scaler LinkedIn, is a Linux kernel feature called “control groups” used with most containers to assign resources. In an analysis based on several months of “pressure testing,” Zhenyun Zhuang, a software Read more…
Steadily advancing neuromorphic computing technology has created high expectations for this fundamentally different approach to computing. Its strengths – like the human brain it attempts to mimic – are pattern recognition (space and time) and inference reasoning. Advocates say it will also be possible to compute at much lower power than current paradigms. At ISC Read more…
If we needed another sign that Intel is serious about mining AI market opportunities, it came today when the chip company announced it had inked a “definitive agreement” to acquire artificial intelligence and deep learning company Nervana Systems. Financial terms haven’t been disclosed yet, but a source familiar with the deal told Recode it’s worth more Read more…
The Message Passing Interface (MPI) is the standard definition of a communication API that has underpinned traditional HPC for decades. The message passing programming represents distributed-memory hardware architectures using processes that send messages to each other. When first standardised in 1993-4, MPI was a major step forward from the many proprietary, system-dependent, and semantically different message-passing libraries that came before it.
July 28 — The FlyElephant team is happy to announce the release of the platform FlyElephant 2.0, with following updates: internal expert community, collaboration on projects, public tasks, Docker and Jupyter support, a new file storage system and work with HPC clusters. FlyElephant is a platform for data scientists, engineers and scientists, which provides a ready-computing infrastructure for Read more…
A relatively new architecture explicitly designed for parallelism – Swarm – based on work at MIT has shown promise for substantially speeding up classes of applications (graphs, for example) and decreasing the programming burden to achieve parallelism. The work, recounted in a recent paper, Unlocking Ordered Parallelism with the Swarm Architecture, bucks conventional wisdom and Read more…
Momentum for open source hardware made a significant advance this week with the launch of startup SiFive and its open source chip platforms based on the RISC-V instruction set architecture. The founders of the fabless semiconductor company — Krste Asanovic, Andrew Waterman, and Yunsup Lee — invented the free and open RISC-V ISA at the University of California, Berkeley, six years ago. The progression of RISC-V and the launch of SiFive opens the door to a new way of chip building that skirts prohibitive licensing costs and lowers the barrier to entry…
The long percolating discussion over ‘co-development’ and how best it should be undertaken has gained new urgency in the race towards exascale computing. At a workshop held at ISC2016 last month – Form Follows Function: Do algorithms and applications challenge or drag behind the hardware evolution? – several distinguished panelists offered varying viewpoints. Yesterday, session organizer Tobias Weinzierl posted a summary synopsis of the workshop discussion on arXiv.org. Weinzierl (Durham University) and co-organizer Michael Bader (Technische Universität München) are active participants in the ExaHyPE project (An Exascale Hyperbolic PDE (partial differential equation) Engine, funded by EU’s Horizon 2020 program).
Sometimes lost in the discussion around big data is the fact that big science has long generated huge data sets. “In fact, large-scale simulations that run on leadership-class supercomputers work at such high speeds and resolution that they generate unprecedented amounts of data. The size of these datasets—ranging from a few gigabytes to hundreds of Read more…
Seventy-one years ago, on July 16, 1945, an incredible explosion lit up the New Mexico night sky. This was the Trinity Test, the world’s first nuclear detonation, and it marked the beginning of the Nuclear Age. It also ushered in the age of supercomputers, which essentially began with weapons science at Los Alamos National Laboratory (LANL). Now a new Trinity, a next generation Cray XC supercomputer is about to take center stage to help the national security labs achieve their primary mission – to provide the nation with a safe, secure and effective nuclear deterrent.
CAMBRIDGE, Mass., July 1 — “Julia is a great tool.” That’s what Nobel Laureate Thomas J. Sargent told 250 engineers, computer scientists, programmers, and data scientists during the third annual JuliaCon held at MIT’s Computer Science and Artificial Intelligence Labs. This year’s JuliaCon was the biggest yet, and featured presentations describing how Julia is being used Read more…
In the last year or so, I’ve had several academic researchers ask me whether I thought it was a good idea for them to develop a tool to automatically convert OpenACC programs to OpenMP 4 and vice versa. In each case, the motivation was that some systems had OpenMP 4 compilers (x86 plus Intel Xeon Phi Knights Corner) and others had OpenACC (x86 plus NVIDIA GPU or AMD GPU), and someone wanting to run a program across both would need two slightly different programs. In each case, the proposed research sounded like a more-or-less mechanical translation process, something more like a sophisticated awk script, and that’s doomed from the start. I will explain below in more detail how I came to this conclusion.
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