Exascale FY18 Budget – The Senate Provides Their Input

In the federal budgeting world, “regular order” is a meaningful term that is fondly remembered by members of both the Congress and the Executive Branch. Regular order is the established proce

By Alex R. Larzelere

Making Cloud Bursting a Reality

To stay ahead of the competition, businesses today must run increasingly intricate modeling and simulation algorithms and perform more sophisticated analysis on larger datasets. And they need the

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India Plots Three-Phase Indigenous Supercomputing Strategy

Additional details on India's plans to stand up an indigenous supercomputer came to light earlier this week. As reported in the Indian press, the Rs 4,500-crore (~$675 million) supercomputing pro

By Tiffany Trader

Tuning InfiniBand Interconnects Using Congestion Control

InfiniBand is among the most common and well-known cluster interconnect technologies. However, the complexities of an InfiniBand (IB) network can frustrate the most experienced cluster administra

By Adam Dorsey

Highlights from ISC High Performance 2017

View the news and highlights from this year’s ISC High Performance 2017 in Frankfurt, Germany.

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Nvidia, Baidu Expand AI Partnership 

July 5, 2017

Today at its developer conference in Beijing, Baidu announced a broadening of its AI partnership with Nvidia, including plans to bring Nvidia’s recently annou Read more…

By Doug Black

Optimizing Codes for Heterogeneous HPC Clusters Using OpenACC

July 3, 2017

Looking at the Top500 and Green500 ranks, one clearly realizes that most HPC systems are heterogeneous architecture using COTS (Commercial Off-The-Shelf) hardware, combining traditional multi-core CPUs with massively parallel accelerators, such as GPUs and MICs. With processor frequencies now hitting a solid wall, the only truly open avenue for riding today the Moore’s law is increasing hardware parallelism in several different ways: more computing nodes, more processors in each node, more cores within each processor, and longer vector instructions in each core. Read more…

By Enrico Calore et. al.

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

June 29, 2017

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms Read more…

By James Reinders

The EU Human Brain Project Reboots but Supercomputing Still Needed

June 26, 2017

The often contentious, EU-funded Human Brain Project whose initial aim was fixed firmly on full-brain simulation is now in the midst of a reboot targeting a mor Read more…

By John Russell

AMD Charges Back into the Datacenter and HPC Workflows with EPYC Processor

June 20, 2017

AMD is charging back into the enterprise datacenter and select HPC workflows with its new EPYC 7000 processor line, code-named Naples, announced today at a “g Read more…

By John Russell

OpenACC Shows Growing Strength at ISC

June 19, 2017

OpenACC is strutting its stuff at ISC this year touting expanding membership, a jump in downloads, favorable benchmarks across several architectures, new staff Read more…

By John Russell

In Memoriam: Jean Sammet Computing Pioneer and First Women President of ACM

June 6, 2017

Jean E. Sammet, a pioneering American computer scientist who developed the FORMAC programming language and who served as the first female president of ACM (Asso Read more…

By John Russell

PGAS Use will Rise on New H/W Trends, Says Reinders

May 25, 2017

If you have not already tried using PGAS, it is time to consider adding PGAS to the programming techniques you know. Partitioned Global Array Space, commonly kn Read more…

By James Reinders

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