HPCwire Exascale Edition

Editors

Thomas Sterling, Ph.D
Thomas Sterling, Ph.D

Professor of Computer Science at Indiana University, a Faculty Associate at California Institute of Technology, and a Distinguished Visiting Scientist at Oak Ridge National Laboratory

Bill Gropp, Ph.D
Bill Gropp, Ph.D

Professor of Computer Science at the University of Illionois Urbana-Champaign

The HPCwire Exascale Edition reports to the HPC community on advances contributing to progress towards exascale computing to achieve partical trans-exaflops performance regime. Managed by luminary guest editors, Thomas Sterling and Bill Gropp, this section intends to serve as a medium for conveying persepctives and opinions on issues of technology, applications, and policies driving directions from leaders in the field.

Top Exascale Feature

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Trinity Wrestles with Knights Landing Programming Challenge with COE

Seventy-one years ago, on July 16, 1945, an incredible explosion lit up the New Mexico night sky. This was the Trinity Test, the world’s first nuclear detonation, and it marked the beginning of the Nuclear Age. It also ushered in the age of supercomputers, which essentially began with weapons science at Los Alamos National Laboratory (LANL). Now a new Trinity, a next generation Cray XC supercomputer is about to take center stage to help the national security labs achieve their primary mission – to provide the nation with a safe, secure and effective nuclear deterrent. Read more…

More Exascale News & Commentary

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ISC Workshop Tackles the Co-development Challenge

The long percolating discussion over ‘co-development’ and how best it should be undertaken has gained new urgency in the race towards exascale computing. At a workshop held at ISC2016 last month – Form Follows Function: Do algorithms and applications challenge or drag behind the hardware evolution? – several distinguished panelists offered varying viewpoints. Yesterday, session organizer Tobias Weinzierl posted a summary synopsis of the workshop discussion on arXiv.org. Weinzierl (Durham University) and co-organizer Michael Bader (Technische Universität München) are active participants in the ExaHyPE project (An Exascale Hyperbolic PDE (partial differential equation) Engine, funded by EU’s Horizon 2020 program). Read more…
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Weekly Twitter Roundup

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. The tweets that caught our eye this past week are presented below. Check back in next Thursday for an entirely updated list.

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Weekly Twitter Roundup

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. The tweets that caught our eye this past week are presented below. Check back in next Thursday for an entirely updated list.

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Compilers and More: OpenACC to OpenMP (and back again)

In the last year or so, I’ve had several academic researchers ask me whether I thought it was a good idea for them to develop a tool to automatically convert OpenACC programs to OpenMP 4 and vice versa. In each case, the motivation was that some systems had OpenMP 4 compilers (x86 plus Intel Xeon Phi Knights Corner) and others had OpenACC (x86 plus NVIDIA GPU or AMD GPU), and someone wanting to run a program across both would need two slightly different programs. In each case, the proposed research sounded like a more-or-less mechanical translation process, something more like a sophisticated awk script, and that’s doomed from the start. I will explain below in more detail how I came to this conclusion. Read more…
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MANGO Project Tackles Power, Performance and Predictability for Future HPC

Under the H2020 High Performance Computing call (Towards exascale high performance computing) MANGO project was awarded funding of 5.8 million euro for three years of research till October 2018. Coordinated by prof. Jose Flich from University of Valencia, consortium includes École polytechnique fédérale de Lausanne, Politecnico di Milano, University of Zagreb, Centro Regionale Information Communication Technology and industrial partners: Eaton Corporation, Pro Design Electronic GmbH, Thales Group and Philips. Read more…

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Thomas Sterling’s ISC 2016 Closing Keynote

Capturing the sparkle, wit, and selective skewering in Thomas Sterling’s annual closing ISC keynote is challenging. This year was his 13th, which perhaps conveys the engaging manner and substantive content he delivers. Like many in the room, Sterling is an HPC pioneer as well as the director of CREST, the Center for Research in Extreme Scale Technologies, Indiana University. In his ISC talk, Sterling holds up a mirror to the HPC world, shares what he sees, and invites all to look in as well and see what they may. Read more…
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ISC 2016 Twitter Roundup

To celebrate ISC 2016, we’ve brought back our ISC-themed Twitter Roundup. For those unable to attend the event in beautiful Frankfurt, Germany, we hope this list will shed some light onto some of the excitement that’s occurring. The tweets that grabbed our attention today are provided below. We hope everyone enjoyed the event and wish you all a safe trip home. See you next year! Read more…

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ISC 2016 Twitter Roundup

To celebrate ISC 2016, we’ve brought back our ISC-themed Twitter Roundup. For those unable to attend the event in beautiful Frankfurt, Germany, we hope this list will shed some light onto some of the excitement that’s occurring. The tweets that grabbed our attention today are provided below and check back in on Wednesday for our final ISC 2016 Twitter Roundup.

Mellanox and PNNL Announce Joint Collaboration to Design Exascale System

FRANKFURT, Germany, June 20 — Mellanox Technologies, Ltd. (NASDAQ: MLNX), a leading supplier of high-performance, end-to-end interconnect solutions for data center servers and storage systems today announced a joint technology collaboration with Pacific Northwest National Laboratory (PNNL) to architect, design and explore technologies for future Exascale platforms. The agreement will explore the advanced capabilities of Mellanox interconnect technology while focusing on a new generation of in-network computing architecture and the laboratory application requirements. Read more…

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What Knights Landing Is Not

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion.

I have found that everything is clear, when we really understand that Knights Landing is an Intel processor. That makes it NOT Knights Corner. That makes it NOT a GPU. Read more…