Exascale and Beyond: Pushing the HPC Envelope

By John Russell

June 1, 2015

Today, HPCwire is launching our latest effort to keep pace with progress – the HPCwire Exascale Edition – which is being led by two very distinguished members of the HPC community, Dr. Thomas Sterling and Dr. William Gropp. These names are no doubt familiar to most of you. I’ve included brief bios below, but they scarcely capture the scope of activities and influence exerted by Dr. Sterling and Dr. Gropp.

For nearly 30 years, HPCwire’s mission has been – and remains – to stand watch over the vanguard of high performance computing. Our tagline says simply, Covering the Fastest Computers in the World and the People Who Run Them.

At first this meant covering a fairly small cadre of HPC thinkers and doers mostly hanging out in government and academic labs with a few commercial exceptions here and there. They were determined to push computing forward and tackle the most difficult computational problems in the world. Today, the HPC community is considerably larger, but no less impressive and still pressing forward for progress.

HPC progress, of course, has always been uneven. Periods of incremental improvements, interrupted by steep barriers requiring step-function advances or conversely suddenly propelled forward by unexpected new discovery, and then followed again by incremental gains. Always fascinating.

The timing for this launch is right. After years of discussion, the technology and funding communities are both mobilizing around Exascale. Maintaining a lead in HPC and supercomputing – it’s now clearly recognized – is a necessary ingredient for commercial/national competitiveness and scientific progress. What was a trickle of funding for Exascale is becoming a meaningful stream as evidenced by the FY2016 budget submitted by the Obama administration.

At DOE’s Office of Science, the biggest spender on HPC, the request for dedicated exascale funding at the four DOE crosscuts – Advanced Scientific Computing Research (ASCR), Basic Energy Sciences (BES), Biological and Environmental Research (BER), and Safeguards and Security – jumped from $99,000,000 (FY2015) to $208,624,000 (FY2016) – not a bad raise; if approved of course. Overall the FY2016 request for R&D spending is up more than 5.5% over the last year.

Exascale_readmore copyNo one knows what Congress will do but the direction is clear. The current generation of supercomputers seems headed towards a performance plateau. The scramble is on to solve the challenges and create the next generation of supercomputers – Exascale machines. No one wants to be left behind. HPCwire readers won’t be.

Although the new section is entitled Exascale, it has broader ambitions, which are well described in co-editors Dr. Sterling and Dr. Gropp’s first installment to be published June 8. To give you a flavor of their thinking, I’ve included their outline of intent and plans. We are delighted and honored to have Dr. Sterling and Dr. Gropp lead this initiative.

The Oxford Dictionary defines vanguard as “A group of people leading the way in new developments or ideas.” That sounds right.

SECTION CO-LEADER BIOS

Dr. Thomas Sterling

sterling_thomasDr. Sterling is Chief Scientist and Executive Associate Director of the Center for Research in Extreme Scale Technologies (CREST), and Professor of informatics and computing at Indiana University.

Dr. Sterling’s current research focuses on the ParalleX advanced execution model to guide the development of future generation Exascale hardware and software computing systems as well as the HPX runtime system to enable dynamic adaptive resource management and task scheduling for significant improvements in scalability and efficiency. This research has been conducted through multiple projects sponsored separately by DOE, NSF, DARPA, Army Core of Engineers, and NASA. Since receiving his PhD from MIT in 1984, Sterling has engaged in applied research in fields associated with parallel computing system structures, semantics, design, and operation in industry, government labs, and higher education.

Dr. Sterling has received numerous awards and in 2014 was named a Fellow of the American Association for the Advancement of Science for his efforts to advance science and its applications. Well-known as the “father of Beowulf” for his research in commodity/Linux cluster computing, Dr. Sterling has conducted research in parallel computing including superconducting logic, processor in memory, asynchronous models of computing, and programming interfaces and runtime software. He spent 14 years at NASA as a senior research scientist as well as at Caltech, IDA, and industry. Prior to coming to Indiana University he was on the faculty at Louisiana University  He has a Ph.D. in EE (1984) and S.M. EE (1981) from the Massachusetts Institute of Technology and a B.S. EE from Old Dominion University (1974). He has co-authored six books and holds six patents.

Dr. William Gropp

gropp_billDr. Gropp is the Thomas M. Siebel Chair in Computer Science, Computer Science Department, and Director, Parallel Computing Institute, at the University of Illinois Urban-Champaign.

Dr. Gropp’s work focuses on the use of high performance computing to solve problems that are too hard for other techniques. He has concentrated in two areas: the development of scalable numerical algorithms for partial differential equations (PDEs), especially for the linear systems that arise from approximations to PDEs, and the development of programming models and systems for expressing and implementing highly scalable applications. In each of these areas, Dr. Gropp has led development of software that has been widely adopted including: PETSc, a powerful numerical library for the solution of linear and nonlinear systems of equations; MPI the mostly widely used parallel programming system for large scale scientific computing; and the MPICH implementation of MPI, one of the most widely used and the implementation of choice for the world’s fastest machines.

Dr. Gropp has earned many honors, among them, National Academy of Engineering, Association for Computing Machinery (ACM) Fellow, Institute of Electrical and Electronics Engineers (IEEE) Fellow, and Society for Industrial and Applied Mathematics (SIAM) Fellow. He has a Ph.D. in Computer Science and M.S. in Computer Science from Stanford University; an M.S. in Physics from the University of Washington; and B.S. in Mathematics from Case Western Research University.

HPCWIRE EXASCALE COVERAGE OUTLINE

Goals and Objectives:

  • Report to the HPC community on advances contributing to progress towards exascale computing to achieve practical trans-exaflops performance regime,
  • Serve as a medium for conveying perspectives and opinions on issues of technology, applications, and policies driving directions from leaders in the field,
  • Inform, define, and describe issues, challenges, and conflicts in the future accomplishment of useful exascale computing systems and methods and the establishment of a viable industry and market, and
  • Provide both national and international focus on current and future goals and projects being undertaken for a balanced and comprehensive coverage.

Types of Articles:

  • News pieces reporting on specific exascale-related technology advances and planning activities,
  • Reports on community forums associated with exascale research and development,
  • Editorials on topics that HPCwire considers of value and interest to the emerging HPC/Exascale community,
  • Interviews with leaders and major contributors to the future of exascale computing hardware, software, and planning policy,
  • Contributed/solicited op-ed pieces, and
  • Summary overviews of technical papers, possibly provided at request by the original authors.

Topical Areas of Interest (not limited to):

  • Hardware device technologies,
  • Architectures for processor cores and systems,
  • Advanced parallel programming models and methods; both intermediate and long term,
  • Exascale applications and algorithms for numeric and big data problems,
  • Focus meetings on exascale related subjects,
  • Highly scalable system software including innovative runtime systems and new operating systems’ advances,
  • Active methods for fault tolerance and power conservation,
  • National and international plans and programs, and
  • Beyond exascale (e.g., quantum computing, Neuromorphic computing).
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