HPCwire Exascale Edition

Editors

Thomas Sterling, Ph.D

Professor of Computer Science at Indiana University, a Faculty Associate at California Institute of Technology, and a Distinguished Visiting Scientist at Oak Ridge National Laboratory

Bill Gropp, Ph.D

Professor of Computer Science at the University of Illionois Urbana-Champaign

The HPCwire Exascale Edition reports to the HPC community on advances contributing to progress towards exascale computing to achieve partical trans-exaflops performance regime. Managed by luminary guest editors, Thomas Sterling and Bill Gropp, this section intends to serve as a medium for conveying persepctives and opinions on issues of technology, applications, and policies driving directions from leaders in the field.

Top Exascale Feature

Thomas Sterling

Thomas Sterling’s ISC 2016 Closing Keynote

Capturing the sparkle, wit, and selective skewering in Thomas Sterling’s annual closing ISC keynote is challenging. This year was his 13th, which perhaps conveys the engaging manner and substantive content he delivers. Like many in the room, Sterling is an HPC pioneer as well as the director of CREST, the Center for Research in Extreme Scale Technologies, Indiana University. Read more…

More Exascale News & Commentary

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ISC 2016 Twitter Roundup

To celebrate ISC 2016, we’ve brought back our ISC-themed Twitter Roundup. For those unable to attend the event in beautiful Frankfurt, Germany, we hope this list will shed some light onto some of the excitement that’s occurring. The tweets that grabbed our attention today are provided below. We hope everyone enjoyed the event and wish you all a safe trip home. See you next year! Read more…

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ISC 2016 Twitter Roundup

To celebrate ISC 2016, we’ve brought back our ISC-themed Twitter Roundup. For those unable to attend the event in beautiful Frankfurt, Germany, we hope this list will shed some light onto some of the excitement that’s occurring. The tweets that grabbed our attention today are provided below and check back in on Wednesday for our final ISC 2016 Twitter Roundup.

Mellanox and PNNL Announce Joint Collaboration to Design Exascale System

FRANKFURT, Germany, June 20 — Mellanox Technologies, Ltd. (NASDAQ: MLNX), a leading supplier of high-performance, end-to-end interconnect solutions for data center servers and storage systems today announced a joint technology collaboration with Pacific Northwest National Laboratory (PNNL) to architect, design and explore technologies for future Exascale platforms. The agreement will explore the advanced capabilities of Mellanox interconnect technology while focusing on a new generation of in-network computing architecture and the laboratory application requirements. Read more…

Intel KNL graphic

What Knights Landing Is Not

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion.

I have found that everything is clear, when we really understand that Knights Landing is an Intel processor. That makes it NOT Knights Corner. That makes it NOT a GPU. Read more…

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Dongarra Honored with Pair of Prestigious Supercomputing Awards

Jack Dongarra, one of today’s most distinguished HPC leaders, is adding two awards to his long list. The Association for Computer Machinery (ACM) recently honored Dongarra with the High Performance Parallel and Distributed Computing Achievement Award at the annual High Performance and Distributed Computing Conference in Kyoto, Japan, while the Institute of Electrical and Electronics Engineers (IEEE) will bestow him with the Super Computing (SC) 2016 Test of Time Award at its conference in November. Read more…
OpenACC

OpenACC Adds Support for OpenPOWER; Touts Growing Traction

In a show of strength leading up to ISC the OpenACC standards group today announced its first OpenPOWER implementation, the addition of three new members – University of Illinois, Brookhaven National Laboratory, and Stony Brook University – and details of its expanding 2016 training schedule. Michael Wolfe, technical director of OpenACC, also talked with HPCwire about thorny compiler challenges still remaining as... Read more…
Sequoia at LLNL

How Lawrence Livermore Is Facing Exascale Power Demands

The old adage “you cannot improve what you do not measure" is fresh again in the age of ubiquitous data. When considering the challenges of exascale computing, power is right at the top of the list and the major leadership-class centers want to make sure they're doing everything they can to manage the demands of power today - which can run as high as 10 MW at peak for the largest machines - and in the coming exascale era, when the number could be three times that high. At loads of this magnitude, the largest HPC facilities need to have all the relevant power data within arm's reach. Read more…
James Reinders

Exiting Intel, James Reinders Offers a Brief Personal Retrospective

You may have heard that Intel has encouraged “long timers” (like me) to consider early retirement. Well, the offer was convincing for me. After 10,001 days at Intel, it is time for me to start the next phase of my life. I've accepted the “ERP offer” (early retirement) with my last day being June 24, 2016 (exactly 10,000 days after my start date). I’ll be in the office as much as needed to help transitions and wrap things up. Let me know if you need/want anything from me as I finish up. Read more…
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Weekly Twitter Roundup

Here at HPCwire, we aim to keep the HPC community apprised of the most relevant and interesting news items that get tweeted throughout the week. The tweets that caught our eye this past week are presented below. Check back in next Thursday for an entirely updated list.

Altera Stratix

ORNL Researchers Create Framework for Easier, Effective FPGA Programming

Programmability and portability problems have long inhibited broader use of FPGA technology. FPGAs are already widely and effectively used in many dedicated applications (accelerated packet processing, for example), but generally not in situations that require ‘reconfiguring’ the FPGA to accommodate different applications. A group of researchers from Oak Ridge National Laboratory is hoping to change that. Read more…