Quadrics Delivers Integral Interconnection

By Nicole Hemsoth

November 4, 2005

HPCwire recently sat down with Moray McLaren, research and development manager at Quadrics Ltd., a leading supplier and developer of high performance networking products and resource management software. The company's applied advanced technology builds clusters that deliver supercomputing levels of performance and reliability. Its QsNet products are based on internally developed ASICs, firmware and software technologies. With a fine track record of working in partnership with other HPC companies as well as organizations such as Lawrence Livermore and Los Alamos National Laboratories, the Pittsburgh Supercomputer Center and Pacific Northwest National Laboratory, Quadrics is at the forefront of helping solve some of the world's most complex computational challenges.

HPCwire: Interconnect vendors such as Quadrics make a lot of their low message latency these days, but how far is this really a measure of capability of an interconnect?

McLaren: Simple latency measurements can give an indication of the potential of an interconnect, but you need to be careful that they are measured in the way that the interconnect will actually be used in the final system. For example, latency is typically measured across just a pair nodes, but when the final system scales up to thousands [of nodes], then you need to consider scaling in both the hardware and software. It's fairly obvious the worst-case hardware latency across a larger network will be higher as you have to traverse more switches, but in some cases the software latencies are higher too since they have to employ different buffer structures for larger scale networks. At Quadrics, we use the same software across all sizes of network. We have ultra low hop latency in our switch so as to reduce the hardware scaling factor

HPCwire: So does the choice of MPI stack effect the measured latency?

McLaren: Surprisingly, not as much as you would think. At Quadrics, we support the Scali, Intel and HP multi-platform MPIs. The simple end-to-end latency is similar across all of them. The Scali and Intel implementations map onto the DAPL abstraction layer. Since the basic transfer mechanism is a remote write operation, which maps very closely onto the mechanisms of the base hardware, there's little overhead here. The problem with MPI implementations that are based on simple puts is that they required order(N) buffer space. This is acceptable for systems of a few hundreds of nodes, but on a 1,000-way network, this can be a significant fraction of the node memory. The way around this is to use a common queue, with the network interface allocating the buffer space. This requires more intelligence on the network interface and can add to latency.

HPCwire: How would you expect it to vary with node architecture?

McLaren: The devil is in the detail here. The actual CPU architecture choice — and even to some extent, the bus choice — are not as important as how “close” the IO bus is to the main memory. In common with most vendors, our current best case latencies are measured on the Opteron platform. But this is as much factor of the integration of the Opteron memory system, as to Hypertransport. In fact, our standard QsNet II adapters produce similar low latencies to other NICs developed specifically for Hypertransport. Newer Intel platforms that bring the PCI- Express interface closer to the memory system are starting to close the gap

When you start looking at larger NUMA systems, then it becomes much more complex, since the latency varies depending on which CPU group you are in and the location on the source and destination memory buffer. At Quadrics, we support multiple rails of interconnect. In this case, the software automatically allocates the communication to the lowest latency adapter.

HPCwire: Would using other APIs give deliver a lower latency result?

McLaren: The Cray Shmem message layer is a simple “put get” mechanism and as such maps well onto any interconnect based on put-and-get. The other key advantage is there is no unnecessary sequentialization of messages. In Shmem, there is effectively a relaxed store order model, which gives the hardware the maximum opportunity to handle communications in parallel. For this reason, it's also a good fit for multi-threaded applications that need to communicate.

HPCwire: Quadrics makes a big deal about collectives performance. Why is this important?

McLaren: If you have a code that has been structured to make extensive use of collective operations, then by having a high performance, highly scalable collective implementation, you can insure that the code will scale well to large numbers of nodes. In our collectives implementation, we actually do the double precision floating point operations on the processor embedded in the network interface. This saves the delays of passing results back and forth across the IO bus to the main processor.

HPCwire: Then aren't bandwidth measures much more straightforward?

McLaren: Since bandwidth is measured over large messages, it is typically less sensitive to software issues. However, you need to watch for people quoting throughput bandwidth, for where a number of simultaneous transfers are used to saturate the link, compared to the bandwidth for a single message transfer. As the message length becomes very large, you can start to run into limitations with the size of mapping hardware or with lock down caches. On Quadrics NICs, we implement a full Memory Management Unit capable of mirroring the main processors VM mappings to avoid this limitation.

HPCwire: So given the limitations of simple benchmarks, wouldn't it be better to test everything with the final applications?

McLaren: For limited size systems, this is indeed preferable, but for the very largest systems this just isn't practical. The good thing about the more straightforward communications benchmarks is that, for a well designed interconnect, the scaling performance is usually very predictable. When you run a complex application, then Amdahl's law means that predicting the performance is much more complex. However, at least if you start with an platforms designed from the outset for scalability, the programmer can concentrate on any potential issues within the code, without being concerned that a performance problem is an artefact of the underlying hardware.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

HPE Server Shows Low Latency on STAC-N1 Test

February 22, 2017

The performance of trade and match servers can be a critical differentiator for financial trading houses. Read more…

By John Russell

HPC Financial Update (Feb. 2017)

February 22, 2017

In this recurring feature, we’ll provide you with financial highlights from companies in the HPC industry. Check back in regularly for an updated list with the most pertinent fiscal information. Read more…

By Thomas Ayres

Rethinking HPC Platforms for ‘Second Gen’ Applications

February 22, 2017

Just what constitutes HPC and how best to support it is a keen topic currently. Read more…

By John Russell

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

HPE Extreme Performance Solutions

O&G Companies Create Value with High Performance Remote Visualization

Today’s oil and gas (O&G) companies are striving to process datasets that have become not only tremendously large, but extremely complex. And the larger that data becomes, the harder it is to move and analyze it – particularly with a workforce that could be distributed between drilling sites, offshore rigs, and remote offices. Read more…

IDC: Will the Real Exascale Race Please Stand Up?

February 21, 2017

So the exascale race is on. And lots of organizations are in the pack. Government announcements from the US, China, India, Japan, and the EU indicate that they are working hard to make it happen – some sooner, some later. Read more…

By Bob Sorensen, IDC

ExxonMobil, NCSA, Cray Scale Reservoir Simulation to 700,000+ Processors

February 17, 2017

In a scaling breakthrough for oil and gas discovery, ExxonMobil geoscientists report they have harnessed the power of 717,000 processors – the equivalent of 22,000 32-processor computers – to run complex oil and gas reservoir simulation models. Read more…

By Doug Black

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

HPC Technique Propels Deep Learning at Scale

February 21, 2017

Researchers from Baidu’s Silicon Valley AI Lab (SVAIL) have adapted a well-known HPC communication technique to boost the speed and scale of their neural network training and now they are sharing their implementation with the larger deep learning community. Read more…

By Tiffany Trader

IDC: Will the Real Exascale Race Please Stand Up?

February 21, 2017

So the exascale race is on. And lots of organizations are in the pack. Government announcements from the US, China, India, Japan, and the EU indicate that they are working hard to make it happen – some sooner, some later. Read more…

By Bob Sorensen, IDC

TSUBAME3.0 Points to Future HPE Pascal-NVLink-OPA Server

February 17, 2017

Since our initial coverage of the TSUBAME3.0 supercomputer yesterday, more details have come to light on this innovative project. Of particular interest is a new board design for NVLink-equipped Pascal P100 GPUs that will create another entrant to the space currently occupied by Nvidia's DGX-1 system, IBM's "Minsky" platform and the Supermicro SuperServer (1028GQ-TXR). Read more…

By Tiffany Trader

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

Drug Developers Use Google Cloud HPC in the Fight Against ALS

February 16, 2017

Within the haystack of a lethal disease such as ALS (amyotrophic lateral sclerosis / Lou Gehrig’s Disease) there exists, somewhere, the needle that will pierce this therapy-resistant affliction. Read more…

By Doug Black

Azure Edges AWS in Linpack Benchmark Study

February 15, 2017

The “when will clouds be ready for HPC” question has ebbed and flowed for years. Read more…

By John Russell

Is Liquid Cooling Ready to Go Mainstream?

February 13, 2017

Lost in the frenzy of SC16 was a substantial rise in the number of vendors showing server oriented liquid cooling technologies. Three decades ago liquid cooling was pretty much the exclusive realm of the Cray-2 and IBM mainframe class products. That’s changing. We are now seeing an emergence of x86 class server products with exotic plumbing technology ranging from Direct-to-Chip to servers and storage completely immersed in a dielectric fluid. Read more…

By Steve Campbell

Cray Posts Best-Ever Quarter, Visibility Still Limited

February 10, 2017

On its Wednesday earnings call, Cray announced the largest revenue quarter in the company’s history and the second-highest revenue year. Read more…

By Tiffany Trader

For IBM/OpenPOWER: Success in 2017 = (Volume) Sales

January 11, 2017

To a large degree IBM and the OpenPOWER Foundation have done what they said they would – assembling a substantial and growing ecosystem and bringing Power-based products to market, all in about three years. Read more…

By John Russell

US, China Vie for Supercomputing Supremacy

November 14, 2016

The 48th edition of the TOP500 list is fresh off the presses and while there is no new number one system, as previously teased by China, there are a number of notable entrants from the US and around the world and significant trends to report on. Read more…

By Tiffany Trader

Lighting up Aurora: Behind the Scenes at the Creation of the DOE’s Upcoming 200 Petaflops Supercomputer

December 1, 2016

In April 2015, U.S. Department of Energy Undersecretary Franklin Orr announced that Intel would be the prime contractor for Aurora: Read more…

By Jan Rowell

D-Wave SC16 Update: What’s Bo Ewald Saying These Days

November 18, 2016

Tucked in a back section of the SC16 exhibit hall, quantum computing pioneer D-Wave has been talking up its new 2000-qubit processor announced in September. Forget for a moment the criticism sometimes aimed at D-Wave. This small Canadian company has sold several machines including, for example, ones to Lockheed and NASA, and has worked with Google on mapping machine learning problems to quantum computing. In July Los Alamos National Laboratory took possession of a 1000-quibit D-Wave 2X system that LANL ordered a year ago around the time of SC15. Read more…

By John Russell

Enlisting Deep Learning in the War on Cancer

December 7, 2016

Sometime in Q2 2017 the first ‘results’ of the Joint Design of Advanced Computing Solutions for Cancer (JDACS4C) will become publicly available according to Rick Stevens. He leads one of three JDACS4C pilot projects pressing deep learning (DL) into service in the War on Cancer. Read more…

By John Russell

IBM Wants to be “Red Hat” of Deep Learning

January 26, 2017

IBM today announced the addition of TensorFlow and Chainer deep learning frameworks to its PowerAI suite of deep learning tools, which already includes popular offerings such as Caffe, Theano, and Torch. Read more…

By John Russell

HPC Startup Advances Auto-Parallelization’s Promise

January 23, 2017

The shift from single core to multicore hardware has made finding parallelism in codes more important than ever, but that hasn’t made the task of parallel programming any easier. Read more…

By Tiffany Trader

CPU Benchmarking: Haswell Versus POWER8

June 2, 2015

With OpenPOWER activity ramping up and IBM’s prominent role in the upcoming DOE machines Summit and Sierra, it’s a good time to look at how the IBM POWER CPU stacks up against the x86 Xeon Haswell CPU from Intel. Read more…

By Tiffany Trader

Leading Solution Providers

Nvidia Sees Bright Future for AI Supercomputing

November 23, 2016

Graphics chipmaker Nvidia made a strong showing at SC16 in Salt Lake City last week. Read more…

By Tiffany Trader

BioTeam’s Berman Charts 2017 HPC Trends in Life Sciences

January 4, 2017

Twenty years ago high performance computing was nearly absent from life sciences. Today it’s used throughout life sciences and biomedical research. Genomics and the data deluge from modern lab instruments are the main drivers, but so is the longer-term desire to perform predictive simulation in support of Precision Medicine (PM). There’s even a specialized life sciences supercomputer, ‘Anton’ from D.E. Shaw Research, and the Pittsburgh Supercomputing Center is standing up its second Anton 2 and actively soliciting project proposals. There’s a lot going on. Read more…

By John Russell

Tokyo Tech’s TSUBAME3.0 Will Be First HPE-SGI Super

February 16, 2017

In a press event Friday afternoon local time in Japan, Tokyo Institute of Technology (Tokyo Tech) announced its plans for the TSUBAME3.0 supercomputer, which will be Japan’s “fastest AI supercomputer,” Read more…

By Tiffany Trader

IDG to Be Bought by Chinese Investors; IDC to Spin Out HPC Group

January 19, 2017

US-based publishing and investment firm International Data Group, Inc. (IDG) will be acquired by a pair of Chinese investors, China Oceanwide Holdings Group Co., Ltd. Read more…

By Tiffany Trader

Dell Knights Landing Machine Sets New STAC Records

November 2, 2016

The Securities Technology Analysis Center, commonly known as STAC, has released a new report characterizing the performance of the Knight Landing-based Dell PowerEdge C6320p server on the STAC-A2 benchmarking suite, widely used by the financial services industry to test and evaluate computing platforms. The Dell machine has set new records for both the baseline Greeks benchmark and the large Greeks benchmark. Read more…

By Tiffany Trader

What Knights Landing Is Not

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion. Read more…

By James Reinders, Intel

KNUPATH Hermosa-based Commercial Boards Expected in Q1 2017

December 15, 2016

Last June tech start-up KnuEdge emerged from stealth mode to begin spreading the word about its new processor and fabric technology that’s been roughly a decade in the making. Read more…

By John Russell

Intel and Trump Announce $7B for Fab 42 Targeting 7nm

February 8, 2017

In what may be an attempt by President Trump to reset his turbulent relationship with the high tech industry, he and Intel CEO Brian Krzanich today announced plans to invest more than $7 billion to complete Fab 42. Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Share This