For the 2nd year running the UK National HPC service at the University of Manchester in collaboration with the Ohio Supercomputer Centre (OSC), hosted a technical symposium, on reconfigurable computing with Field Programmable Gate Arrays (FPGAs). The symposium, sponsored by SGI, Intel and OSC Springfield, provided a forum to exchange experiences and explore possibilities, of using reconfigurable computing to accelerate software applications. Several of the speakers described their own experiences with FPGAs. The Symposium was preceded, by a hands-on, workshop on how to program FPGAs for HPC applications. It was supervised, by Matthias Fouquet-Lapar, from SGI and Stefan Möhl, from Mitrionics. Symposium speakers and many of the attendees enthused about this new area of computing, claiming plenty of promise. In fact one participant of the workshop, without prior knowledge of FPGAs, developed a working design of a medical imaging algorithm and ran it on an SGI system with FPGAs. It is that easy!

Speakers included experts from SGI, Nallatech, Mitrionics, Ohio Supercomputer Centre (OSC), Oak Ridge National Laboratory (ORNL), NCSA, SRC Inc., and FPGA users and researchers from several UK universities including the Edinburgh Parallel Computing Centre, EPCC.

To recap, FPGAs are part of a class of devices known as PLDs (Programmable Logic Devices), which can be programmed in the field after manufacture. Reconfigurable computing is a general-purpose hardware agent configured to carry out a specific task, but can be reconfigured on-demand, to carry out other specific tasks. They enable implementation of an algorithm for a particular function in hardware.

FPGAs are found embedded in many industrial applications, e.g. electrical power grids, space robots such as the spirit and opportunity Rover landed on Mars and also in computer PCI and I/O PADs. Of course security agencies have been using handcrafted gate arrays for at least 20 years for encryption/decryption analysis. Advances in technology allow newer FPGAs to have many more gates and tightly integrated interface functions. They are now also included in some mainstream computers such as the Cray XD1 and the SGI Altix systems, as co-processors for accelerating specific applications. SRC Inc., Seymour Cray's last business venture, offers a system SRC-6/7 relying heavily on FPGAs for computation. At least one other vendor is poised to announce entry into this field, in the near future.

The programming paradigm consists of identifying a kernel from a large application legacy code, convert the underlying algorithm into FPGA binary circuit design and execute this in hardware. A number of high-level language toolkits have been developed to make this process relatively easy for the user. 

For certain types of computations needing integer or fixed point arithmetic the benefits of FPGAS can be very significant, two orders of magnitude speed improvement compared to using a conventional cluster CPU. Identifying the inherent fine parallelism of the algorithm and utilizing the hardware gates, to concisely perform the relevant calculation, often using logical shifts and Boolean operations, achieve this speedup, but remember only for the part executed in an FPGA. The whole application would have a smaller improvement in performance thanks to Amdahl's Law. Nevertheless, some HPC applications, for example cryptography, some chemistry codes, automation, fall into a special class of applications, which can have significant overall performance benefit. Large HPC centers such as ORNL, NCSA are exploring the possibility of using FPGAs to run large applications. Apart from the potential performance gains, FPGAs have low electrical power needs, an added benefit and incentive. Below is a brief synopsis of some of the talks at the symposium to give a flavor of what was said.

Matthias Fouquet-Lapar, principal engineer, at SGI talked about: “Reconfigurable computing within SGI's system architecture.” This talk listed the traditional types of computer CPUs and mentioned the electrical power constraints facing large computing facilities. He then described the Altix 4700 Blade, consisting of the NUMAlink system interconnect, many general-purpose compute nodes, peer-attached general purpose I/O, integrated graphics/visualization and reconfigurable application specific computing (RASC). He addressed the benefits of providing a scalable solution for reconfigurable processing, tightly coupled to the global shared memory architecture, that other processing elements in the system can use.

SGI developed tools and software stack for efficiently integrating reconfigurable technology with general purpose processing. Apart from general tools SGI has an abstraction layer for “wide-scaling.” The user specifies the number of FPGAs, and core SGI services take care for disseminating data across them. These systems are easy to use: “The user writes an application in standard C, identifies computation intense routines, generates a bit stream using SGI core services and uses the language of choice, e.g. create circuit design module using Mitrion-C. This is then executed on FPGAs.

SGI's roadmap is anchored to a heterogeneous system with globally addressable space, low latencies, high bandwidth and fast communication interconnects. Several 3rd party FPGA software language tools (environments) are supported on SGI Altix systems. These include, the Mitrion Virtual Processor and Mitrion Software Development Kit, enabling fast development times by troubleshooting, debugging and optimizing Mitrion Processor designs, before performing a synthesis to produce a circuit design for FPGA, as well as Starbridge Viva (VHDL) and Celoxica. 

Matthias then highlighted some of the challenges facing innovative processors such as FPGAs and how they are to be integrated into HPC. What is the typical usage model in HPC? Should one have optimized libraries encapsulated in dynamic libraries?  Should ISV applications not require re-compilation to use FPGAs? How does the system know when to execute on the local microprocessor, or in the FPGA, taking into account cost of function call and communication overhead. What happens on a multi-user system? There is a need for checkpoint/restart. At the next level, should the Linux kernel understand the concept of different computing paradigms? When dynamically replacing library functions, is there a need to maintain “traditional” exception handling model? E.g. divide by 0, under/overflow, hardware error (memory error). How is an algorithm distributed, across multiple FPGAs and what about a post-mortem error analysis, on core file? As it can be seen from above, there are many unresolved issues.

Stefan Möhl, co-founder of Mitrionics AB, gave a talk titled: “Fast, flexible and effortless programming of FPGAs.” He began his talk encapsulating the FPGA essence, describing it as an empty reconfigurable silicon surface. He said that: “Compared to fixed silicon at the same process technology (90nm) it is about 30 times slower and about 100 times larger per gate, but compared to CPUs it is 10-100 times faster and needs a lot less electrical power.”

Adding FPGAs change the characteristics of a supercomputer, fundamentally. As the FPGA is reconfigurable one is able to design a non von Neumann network topology, specific to the algorithm with one cycle latency. The algorithm is programmed at a very fine-grain parallelism, a single instruction on each node, each node adapted to run its instruction. The architecture transforms sequential instruction scheduling into parallel packet switching.

Stefan went on to describe the top-down solution adopted by Mitrionics. He said: “The Mitrion Virtual Processor and Mitrion Software Development Kit allow supercomputing software applications to be written for FPGAs, easier than existing hardware design and ESL (Electronic System Level) design tools. The Mitrion Platform is an FPGA supercomputing development technology that allows scientists, researchers, and software developers to program FPGAs without hardware design knowledge.” [See Mitrion Press Release 7 February 2006: Mitrionics Enhances FPGA Supercomputing Platform with Diagnostics and Optimization Features].

The philosophy behind the Mitrion system is: “Do not attempt to build hardware directly from a program. Instead, insert a machine between the program and the hardware. Compile the program into code for the machine adapt the machine according to code and instantiate the adapted machine in an FPGA.”

Stefan proceeded to give an interesting color coded graphical demonstration of using Mitrion-C, for specifying and implementing an algorithm. Life science and computational biology performing sequence alignment and digital image analysis are highly represented in Mitrion's customers. Other application areas include chemistry, encryption and automation. The Mitrion FPGA software is available on Nallatech, SGI and the Cray XD1 systems.

Rob Baxter, EPCC gave a presentation titled: “A general purpose 64-FPGA Supercomputer.” He explained that EPCC set up an FPGA HPC Alliance (FHPCA), for developing computing solutions using FPGAs, to deliver higher performance. They plan to achieve this by implementing a large-scale FPGA demonstrator, “Supercomputer.”

The alliance partners are: Algotronix, Alpha Data Parallel Systems, EPCC, the Institute for System Level Integration, Nallatech, Scottish Enterprise and Xilinx. This talk offered some background on the FHPCA and reviewed the current status of the prototype 1 Tflop/s supercomputer project. It covered the current high-level system design and summarized their thinking on a vendor-neutral hardware-abstraction programming model. Being a commercially driven project a key part of the project is application demonstrators. Currently developing prospects in target markets include: Oil and Gas, financial services, life sciences, imaging, modeling and simulation. The key principle of the project is that results are commercially exploitable.

Jon Huppenthal, from Seymour Research Computers, SRC, described their product line, the SRC-6 and their latest SRC-7 system. This system is based on ‘Implicit plus Explicit' architecture. This architecture tightly couples both implicitly controlled dense logic devices, such as microprocessors, with explicitly controlled direct execution logic called MAP. Both processor types are peers on shared memory. The SRC product line has a standard Linux operating system and runs all legacy codes written in standard C and FORTRAN. The ‘Carte Programming Environment' supports standard programming languages C and FORTRAN used today to program MAP and microprocessors. It generates parallel and pipelined logic; includes many third party tools; a synthesizer, place and route and microprocessor compilers are integrated to run from simple MAKE files. It allows multi-FPGA and multi-MAP applications, has a global resource manager and supports single or multi-user environments.

The SRC-7 has a very respectable Hi-Bar interconnect with high bandwidth. Jon Huppenthal gave some benchmark results, for example, the SANDER module in AMBER, a molecular dynamics code. Benchmarks from the molecular dynamics suite used cases with 24,000 to 194,000 atoms. Data movement used 24 bytes per atom per time step in single precision data (32-bit elements). Data was streamed from off-board common memory. The speedup for time step calculation was 17x and time to solution was 7x. He went on to claim that: “A single series H MAP performance is equivalent to 16 AMD Opterons, or 16 IBM Power or Blue Gene/L processors.

In a separate benchmark, they looked at 3-D FFT performance, using complex double precision data (128 bit elements). Data was again streamed from off-board common memory. It mapped 4 double precision floating-point butterflies per user chip. This took 27 ms time to solution including all data movement. Again, he claimed that: “A single series H MAP performance, is equivalent to a 64 nodes Blue Gene/L system.”

These are impressive results and they seem to be corroborated by Dave Pointer, from the Innovative Systems Laboratory (ISL) at NCSA, during his talk at this symposium. Dave is heading the ISL team evaluating emerging technologies, serving as a two-way bridge between vendors and application scientists. They are looking at systems and technologies of 1 to 5 years from possible deployment into production. The team evaluates emerging systems with real applications and data sets. They also collaborate with vendors to influence future developments.

They have already ported a number of application codes on the SRC-6 system and are very encouraged. Dave concluded: “We demonstrated that the potential exists for reconfigurable computing to serve floating-point scientific applications. For example, molecular dynamics code NAMD, using 100 MHz FPGA achieves 3x of a 2.8 GHz CPU. Application programmers can program HPRC systems without knowledge of hardware.”

Another application investigated is a distance transform algorithm, used to isolate image regions for further processing. After 3 days work this achieved 18x speedup. Dave's team is looking for an application from the national reconnaissance office, or an application for MRI or XRAY analysis. They are also tackling the search for dark matter algorithms, which they already showed it has potential.

He optimistically claimed: “With a lot of work, technology will mature in roughly one year and the business value case will mature in roughly two years, enabling sustained petaflop/s computing for scientific applications, in two to three years.”

Eric Lord, from Nallatech presented a case study of lattice gas simulation. This was done to demonstrate it is worthwhile exploiting complex models using tools and techniques currently available on FPGAs. He claimed a 16x speedup from a 1GHz PC, using comparable development time. As expected the conclusion was, that this is possible and worthwhile.

Since last year's report from Manchester, Olaf Storaasli moved from NASA Langley and is now heading the future technology team at ORNL. He is also looking at demonstrating how FPGAs, Cell and Array (ClearSpeed), PIM and other nascent technologies, can be used in mainstream HPC applications. At this juncture the direction of the industry is very volatile, as is gearing itself for petaflop/s computing promised for year 2009/10. From his work at NASA and ORNL, Olaf said that: “FPGAs are substantially outstripping microprocessor performance, for certain applications.” 

HPC is always keen to exploit innovation if it provides real performance gains, but are FPGAs the next disruptive technology to deliver for HPC? Several speakers claimed that FPGAs deliver significant performance gains for some applications, within the known and tested general-purpose computer environment. The tool sets to instrument FPGAs, are getting more mature promising to deliver seamless utilization in the future. Double precision (64-bit) floating-point arithmetic, although it can be done using the FPGA fabric, it takes 4x more resources.

The consensus view at the symposium was not if but when FPGAs will be part of HPC. As one speaker said: “Parallel computing took 15 years to mature, so one should not expect miracles with FPGAs.” As more silicon is available to play with, computer architectures are being augmented using normal engineering fashion tradeoffs, integrating specialized devices, FPGAs, Cell, ClearSpeed Array coprocessors, and graphics cards to perform specific functions, enhancing computing power for specific application domains, without leaving the general purpose computing system environment. The future of these explicit devices would depend to a great extend on the path big players (vendors) in the HPC industry opt for, to solve the electrical power constraints.

Finally, the setting up of an open FPGA organization, to collect and develop algorithms on FPGAs for important applications, is progressing. The FPGAs community set up a number of working groups, to address specific issues including developing standards and organizing user forums to promote FPGA technology. Kevin Wohlever, from OSC said they are in the process of finalizing the organization charter before legal incorporation. Anyone interested should visit their web site, www.openfpga.org.

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Copyright (c) Christopher Lazou, HiPerCom Consultants, Ltd., UK. February 2006. Brands and names are the property of their respective owners.