Intel Prepares to Eat AMD’s Launch

By Michael Feldman

August 31, 2007

In a commentary I wrote earlier this month, I talked about how Intel and AMD are preparing themselves for the looming quad-core war that will begin on September 10, when AMD officially launches its Barcelona Opteron processor. The two chipmakers have been busy jockeying for position by leaking pre-launch information about their upcoming quad-core server products.

On Tuesday, CNET’s News.com reported that Intel will announce the availability of its new Xeon MP (multiprocessor) “Tigerton” chips next week, just days before Barcelona’s coming out party. Tigerton represents the Core microarchitecture implementation for the Xeon MP line, which is designed to be used in platforms with four or more processors. The new processors are expected to be offered in a range of clock speeds (up to 2.93GHz) and power envelopes (as low as 50 watts). Next week’s Tigerton launch appears to be timed to blunt the impact of the Barcelona introduction.

At this point, it’s not clear if the initial Barcelona launch will even include an MP version. It’s likely that AMD will announce only Opterons for dual-processor servers in September. In that case, the new Tigerton will temporarily represent the only path to a four-processor, quad-core x86 server, although Sun currently offers the equivalent in their eight-processor, dual-core Opteron Sun Fire X4600 server. As it stands today, AMD generally dominates the 4P and above x86 server space with its dual-core Opteron 8000 series processors.

The new Tigerton is part of the “Caneland” platform, in which each processor is directly connected to the chipset using separate links. This should alleviate some of the communication bottlenecks and further improve overall performance compared with Intel’s current Xeon MP offering, which is based on the older Netburst architecture. The Opterons, with their HyperTransport links and integrated memory controller, should still retain a performance advantage in applications where main memory access or inter-processor communication is the dominant bottleneck.

Next year however, Intel plans to introduce its Common System Interface, or CSI, and on-chip memory controllers, in an effort to bring its architecture in line with the Opteron computing style. This week’s feature article talks more about CSI and how it will change the Intel/AMD dynamic.

While the Xeon MP is mostly aimed at high-end x86 servers in the enterprise, traditional HPC users may consider Tigerton-based systems if the price, application performance, and power consumption line up correctly. For the same reasons, system vendors may consider building 4P Tigerton-based workstations specifically aimed at the technical computing market.

It will be interesting to see what Intel’s new best buddy, Sun Microsystems, does with the new Xeons and Opterons. Sun will certainly incorporate the quad-core Opterons into its existing AMD-based Sun Fire product line for high performance computing. In fact, Sun doesn’t need to invent new Sun Fire offerings specifically for Barcelona. The quad-core Opterons are plug-compatible with the dual-core version, so existing Sun Fire customers can just buy a bag of new chips and have at it. I’m guessing Sun has other plans for the Tigerton. I wouldn’t be surprised to see those chips turn up in a 4P Sun Blade 6000 offering. There they may find some duty as a high performance computing platform, but more likely in a mixed workload environment, with traditional enterprise computing mixed with HPC.

If the Tigerton launch fails to put a damper on the Barcelona introduction on September 10, Intel has a second chance at the fall Intel Developer Forum (IDF), which takes place September 18-20. Using the IDF stage, Intel can trot out new performance benchmarks, talk about upcoming whiz-bang technology, and just generally remind everyone who invented the x86.

Meanwhile AMD is already setting up some expectations of what lies beyond the Barcelona offerings. In InformationWeek, Alexander Wolfe writes that AMD is planning to quickly jack up the clock speeds of the quad-core Opterons in Q4. This is not a huge surprise. Because of Intel’s new Core architecture and their move to the 45nm process technology later this year, AMD is under a lot of pressure to keep single core performance competitive with its rival. Because Opterons have integrated memory controllers to help with memory performance, AMD doesn’t have to match Xeon clock speed hertz for hertz in order to be competitive in overall performance, but they have to get close.

According to Wolfe, the Barcelona launch will include two processors: a standard 2.0GHz, 95 watt version and a low-power 1.9GHz, 68 watt version. He says AMD will introduce faster versions of each before the end of the year. A higher performance 120 watt processor won’t ship until the fourth quarter. At that point, it’s expected to clock in at 2.3GHz or better. Keep in mind that AMD’s Q4 releases will probably be going up against Intel’s 45nm Penryn processors, which are expected to be available in the same general timeframe. Information leaked by Intel a couple of weeks ago has the top-of-the line Penryn chip at 3.16GHz.

Beyond 2007, AMD is planning to deliver the 45nm “Shanghai” Opterons (dual and quad) in the second half of 2008. As a nod to Intel, these processors will incorporate more cache — 512KB of L2 cache per core and 6MB of unified L3 cache. The Shanghai Opterons will presumably be going up against Intel Xeons with the Nehalem microarchitecture, which will support the new CSI links and integrated memory controllers. If that contest comes to pass, it may prove to be the closest matchup between the two chipmakers in a long time.

—–

As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at [email protected].

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