Intel Touts New Energy-Efficient Circuitry

By Michael Feldman

February 20, 2012

Intel will be figuring prominently at this week’s IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, where researchers will be presenting a raft of emerging technologies — everything from integrated digital radio to optical interconnects. But some of the chipmaker’s most interesting presentations are being devoted to low-power circuitry.

In a prelude to ISSCC, Intel CTO Justin Rattner held a press briefing last week, outlining a couple of energy-focused technologies they’ve been working on. Specifically, Rattner spoke about the ongoing research with near threshold voltage circuitry designs and a new variable precision floating point unit. While both technologies are still confined to the research labs, Intel looks to be grooming them for their commercial debut.

The idea behind near threshold voltage (NTV), said Rattner, is to design circuit logic or memory that can operate at very low power voltage, thereby saving on energy. As its name implies, NTV works at just a notch above the transistor threshold level, that is, the point at which the device would actually shut off. The advantage to this is that transistors exhibits peak energy efficiencies in this NTV range — on the order of 5 to 10 times more efficient than when operating at “normal” levels.

For a microprocessor, this means you can decrease the voltage significantly, enabling a standard CPU, like a Pentium, to be powered by just a few milliwatts. The downside is that as voltage is squeezed, the clock frequency drops, thereby slowing throughput. But since frequency only decreases linearly with voltage, while power decreases quadratically, throughput per watt should be much better.

Another advantage of NTV circuitry is that it enables a much greater dynamic voltage range. So you can crank the clock up and down more easily, thus providing more control over the balance between performance and energy use. This is ideal for settings where the workload is variable, but where you might want to max out performance for at least some of the applications.

Of course, since maximum energy savings comes from keeping the voltages low, it makes more sense to use more (if slower) NTV processors for a given application, as long as you can parallelize your code sufficiently. Rattner said one potential application area for this technology is exascale hardware, where any loss of individual processor performance is naturally compensated for by the scale of the system.

At the Intel Developer Forum last fall, the company demonstrated an NTV prototype, known as Claremont, which was essentially a Pentium chip overlaid with NTV circuitry. At ISSCC this week, they will show how that design can operate between 3MHz and 915MHz, and is able to achieve up to 4.7 times better energy efficiency than a standard chip. At the most conservative voltage levels, the processor is able to run with a mere 2 milliwatts of power.

The NTV technology can also be applied to memory circuits and graphics logic, something Intel will demonstrate at ISSCC with an NTV-tweaked SIMD engine for processor graphics. In this case, since the graphics logic was designed with NTV in mind (unlike the Claremont Pentium-based prototype), the researchers were able to achieve a 9-fold increase in energy efficiency.

Intel is also wrapping low-power technology into floating point logic, one of the biggest energy hogs on microprocessors. Part of the problem is that floating point units operate at maximum precision (or more typically at two levels — single and double precesion) thus wasting computational bandwidth and storage. As Rattner noted that most programmers opt to use the default 64-bit floating point level, not realizing that in most cases, far less precision is required to get the correct answer.

To address the problem, Intel has invented what they call their “Variable Precision Floating Point Unit. The idea here is to build smarts into the hardware such that the computation is confined to the significant digits rather than the programmer-defined value. Intel’s has built an FP unit prototype that automagically right-sizes the floating point computation by using something called certainty tracking to determine the required accuracy.

The prototype has three floating point gears: 24-bit, 12-bit and 6-bit, and uses the certainty tracking to determine which bit width is appropriate. When less digits are warranted, there are fewer bits to shuffle, so not only is energy saved, but performance is increased as well.

Rattner claimed the design is able to cut energy consumption by as much as 50 percent over a conventional FP design. According to Intel, the prototype, which is clocked at 1.45GHz, is able to deliver between 52 and 162 gigaflops/watt. Intel estimates that if they used NTV techniques on their variable precision floating point design, they could realize an additional 7-fold efficiency gain. (For reference, a 20MW exaflop system needs an energy efficiency of just 50 gigaflops/watt, but that includes the entire microprocessor as well as external memory, I/O chips, network fabric, and so on.)

Rattner said the technology is applicable to GPUs (especially for visual computing and traditional graphics) and HPC-type processor designs. In the case of the latter, the implication is that it could be used for Intel’s Many Integrated Core (MIC) processors, which are essentially big floating point processors in an x86 wrapper. In both the graphics and HPC case, the energy efficiency of the floating point hardware is critical to the value proposition of the associated products.

“We have lots of plans for this technology,” said Rattner, “and you can certainly expect to see it as we move out toward the middle of the decade and beyond, where these energy challenges become even more severe than they are today.”

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

ASC18: Final Results Revealed & Wrapped Up

May 17, 2018

It was an exciting week at ASC18 in Nanyang, China. The student teams braved extreme heat, extremely difficult applications, and extreme competition in order to cross the cluster competition finish line. The gala awards ceremony took place on Wednesday. The auditorium was packed with student teams, various dignitaries, the media, and other interested parties. So what happened? Read more…

By Dan Olds

ASC18: Tough Applications & Tough Luck

May 17, 2018

The applications at the ASC18 Student Cluster Competition were tough. Tougher than the $3.99 steak special at your local greasy spoon restaurant. The apps are so tough that even Chuck Norris backs away from them slowly. Read more…

By Dan Olds

Spring Meetings Underscore Quantum Computing’s Rise

May 17, 2018

The month of April 2018 saw four very important and interesting meetings to discuss the state of quantum computing technologies, their potential impacts, and the technology challenges ahead. These discussions happened in Read more…

By Alex R. Larzelere

HPE Extreme Performance Solutions

HPC and AI Convergence is Accelerating New Levels of Intelligence

Data analytics is the most valuable tool in the digital marketplace – so much so that organizations are employing high performance computing (HPC) capabilities to rapidly collect, share, and analyze endless streams of data. Read more…

IBM Accelerated Insights

Mastering the Big Data Challenge in Cognitive Healthcare

Patrick Chain, genomics researcher at Los Alamos National Laboratory, posed a question in a recent blog: What if a nurse could swipe a patient’s saliva and run a quick genetic test to determine if the patient’s sore throat was caused by a cold virus or a bacterial infection? Read more…

Quantum Network Hub Opens in Japan

May 17, 2018

Following on the launch of its Q Commercial quantum network last December with 12 industrial and academic partners, the official Japanese hub at Keio University is now open to facilitate the exploration of quantum applications important to science and business. The news comes a week after IBM announced that North Carolina State University was the first U.S. university to join its Q Network. Read more…

By Tiffany Trader

ASC18: Final Results Revealed & Wrapped Up

May 17, 2018

It was an exciting week at ASC18 in Nanyang, China. The student teams braved extreme heat, extremely difficult applications, and extreme competition in order to cross the cluster competition finish line. The gala awards ceremony took place on Wednesday. The auditorium was packed with student teams, various dignitaries, the media, and other interested parties. So what happened? Read more…

By Dan Olds

Spring Meetings Underscore Quantum Computing’s Rise

May 17, 2018

The month of April 2018 saw four very important and interesting meetings to discuss the state of quantum computing technologies, their potential impacts, and th Read more…

By Alex R. Larzelere

Quantum Network Hub Opens in Japan

May 17, 2018

Following on the launch of its Q Commercial quantum network last December with 12 industrial and academic partners, the official Japanese hub at Keio University is now open to facilitate the exploration of quantum applications important to science and business. The news comes a week after IBM announced that North Carolina State University was the first U.S. university to join its Q Network. Read more…

By Tiffany Trader

Democratizing HPC: OSC Releases Version 1.3 of OnDemand

May 16, 2018

Making HPC resources readily available and easier to use for scientists who may have less HPC expertise is an ongoing challenge. Open OnDemand is a project by t Read more…

By John Russell

PRACE 2017 Annual Report: Exascale Aspirations; Industry Collaboration; HPC Training

May 15, 2018

The Partnership for Advanced Computing in Europe (PRACE) today released its annual report showcasing 2017 activities and providing a glimpse into thinking about Read more…

By John Russell

US Forms AI Brain Trust

May 11, 2018

Amid calls for a U.S. strategy for promoting AI development, the Trump administration is forming a senior-level panel to help coordinate government and industry research efforts. The Select Committee on Artificial Intelligence was announced Thursday (May 10) during a White House summit organized by the Office of Science and Technology Policy (OSTP). Read more…

By George Leopold

Emerging Advanced Scale Tech Trends Focus of Annual Tabor Conference

May 9, 2018

At Tabor Communications' annual Advanced Scale Forum (ASF) held this week in Austin, the focus was on enterprise adoption of HPC-class technologies and high performance data analytics (HPDA). It’s a confab that brings together end users (CIOs, IT planners, department heads) and vendors and encourages... Read more…

By the Editorial Team

Google I/O 2018: AI Everywhere; TPU 3.0 Delivers 100+ Petaflops but Requires Liquid Cooling

May 9, 2018

All things AI dominated discussion at yesterday’s opening of Google’s I/O 2018 developers meeting covering much of Google's near-term product roadmap. The e Read more…

By John Russell

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

How the Cloud Is Falling Short for HPC

March 15, 2018

The last couple of years have seen cloud computing gradually build some legitimacy within the HPC world, but still the HPC industry lies far behind enterprise I Read more…

By Chris Downing

Russian Nuclear Engineers Caught Cryptomining on Lab Supercomputer

February 12, 2018

Nuclear scientists working at the All-Russian Research Institute of Experimental Physics (RFNC-VNIIEF) have been arrested for using lab supercomputing resources to mine crypto-currency, according to a report in Russia’s Interfax News Agency. Read more…

By Tiffany Trader

Inventor Claims to Have Solved Floating Point Error Problem

January 17, 2018

"The decades-old floating point error problem has been solved," proclaims a press release from inventor Alan Jorgensen. The computer scientist has filed for and Read more…

By Tiffany Trader

Researchers Measure Impact of ‘Meltdown’ and ‘Spectre’ Patches on HPC Workloads

January 17, 2018

Computer scientists from the Center for Computational Research, State University of New York (SUNY), University at Buffalo have examined the effect of Meltdown Read more…

By Tiffany Trader

Nvidia Responds to Google TPU Benchmarking

April 10, 2017

Nvidia highlights strengths of its newest GPU silicon in response to Google's report on the performance and energy advantages of its custom tensor processor. Read more…

By Tiffany Trader

Deep Learning at 15 PFlops Enables Training for Extreme Weather Identification at Scale

March 19, 2018

Petaflop per second deep learning training performance on the NERSC (National Energy Research Scientific Computing Center) Cori supercomputer has given climate Read more…

By Rob Farber

AI Cloud Competition Heats Up: Google’s TPUs, Amazon Building AI Chip

February 12, 2018

Competition in the white hot AI (and public cloud) market pits Google against Amazon this week, with Google offering AI hardware on its cloud platform intended Read more…

By Doug Black

Leading Solution Providers

US Plans $1.8 Billion Spend on DOE Exascale Supercomputing

April 11, 2018

On Monday, the United States Department of Energy announced its intention to procure up to three exascale supercomputers at a cost of up to $1.8 billion with th Read more…

By Tiffany Trader

Lenovo Unveils Warm Water Cooled ThinkSystem SD650 in Rampup to LRZ Install

February 22, 2018

This week Lenovo took the wraps off the ThinkSystem SD650 high-density server with third-generation direct water cooling technology developed in tandem with par Read more…

By Tiffany Trader

HPC and AI – Two Communities Same Future

January 25, 2018

According to Al Gara (Intel Fellow, Data Center Group), high performance computing and artificial intelligence will increasingly intertwine as we transition to Read more…

By Rob Farber

Google Chases Quantum Supremacy with 72-Qubit Processor

March 7, 2018

Google pulled ahead of the pack this week in the race toward "quantum supremacy," with the introduction of a new 72-qubit quantum processor called Bristlecone. Read more…

By Tiffany Trader

HPE Wins $57 Million DoD Supercomputing Contract

February 20, 2018

Hewlett Packard Enterprise (HPE) today revealed details of its massive $57 million HPC contract with the U.S. Department of Defense (DoD). The deal calls for HP Read more…

By Tiffany Trader

CFO Steps down in Executive Shuffle at Supermicro

January 31, 2018

Supermicro yesterday announced senior management shuffling including prominent departures, the completion of an audit linked to its delayed Nasdaq filings, and Read more…

By John Russell

Deep Learning Portends ‘Sea Change’ for Oil and Gas Sector

February 1, 2018

The billowing compute and data demands that spurred the oil and gas industry to be the largest commercial users of high-performance computing are now propelling Read more…

By Tiffany Trader

Nvidia Ups Hardware Game with 16-GPU DGX-2 Server and 18-Port NVSwitch

March 27, 2018

Nvidia unveiled a raft of new products from its annual technology conference in San Jose today, and despite not offering up a new chip architecture, there were still a few surprises in store for HPC hardware aficionados. Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Share This