Intel will be figuring prominently at this week’s IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, where researchers will be presenting a raft of emerging technologies — everything from integrated digital radio to optical interconnects. But some of the chipmaker’s most interesting presentations are being devoted to low-power circuitry.
In a prelude to ISSCC, Intel CTO Justin Rattner held a press briefing last week, outlining a couple of energy-focused technologies they’ve been working on. Specifically, Rattner spoke about the ongoing research with near threshold voltage circuitry designs and a new variable precision floating point unit. While both technologies are still confined to the research labs, Intel looks to be grooming them for their commercial debut.
The idea behind near threshold voltage (NTV), said Rattner, is to design circuit logic or memory that can operate at very low power voltage, thereby saving on energy. As its name implies, NTV works at just a notch above the transistor threshold level, that is, the point at which the device would actually shut off. The advantage to this is that transistors exhibits peak energy efficiencies in this NTV range — on the order of 5 to 10 times more efficient than when operating at “normal” levels.
For a microprocessor, this means you can decrease the voltage significantly, enabling a standard CPU, like a Pentium, to be powered by just a few milliwatts. The downside is that as voltage is squeezed, the clock frequency drops, thereby slowing throughput. But since frequency only decreases linearly with voltage, while power decreases quadratically, throughput per watt should be much better.
Another advantage of NTV circuitry is that it enables a much greater dynamic voltage range. So you can crank the clock up and down more easily, thus providing more control over the balance between performance and energy use. This is ideal for settings where the workload is variable, but where you might want to max out performance for at least some of the applications.
Of course, since maximum energy savings comes from keeping the voltages low, it makes more sense to use more (if slower) NTV processors for a given application, as long as you can parallelize your code sufficiently. Rattner said one potential application area for this technology is exascale hardware, where any loss of individual processor performance is naturally compensated for by the scale of the system.
At the Intel Developer Forum last fall, the company demonstrated an NTV prototype, known as Claremont, which was essentially a Pentium chip overlaid with NTV circuitry. At ISSCC this week, they will show how that design can operate between 3MHz and 915MHz, and is able to achieve up to 4.7 times better energy efficiency than a standard chip. At the most conservative voltage levels, the processor is able to run with a mere 2 milliwatts of power.
The NTV technology can also be applied to memory circuits and graphics logic, something Intel will demonstrate at ISSCC with an NTV-tweaked SIMD engine for processor graphics. In this case, since the graphics logic was designed with NTV in mind (unlike the Claremont Pentium-based prototype), the researchers were able to achieve a 9-fold increase in energy efficiency.
Intel is also wrapping low-power technology into floating point logic, one of the biggest energy hogs on microprocessors. Part of the problem is that floating point units operate at maximum precision (or more typically at two levels — single and double precesion) thus wasting computational bandwidth and storage. As Rattner noted that most programmers opt to use the default 64-bit floating point level, not realizing that in most cases, far less precision is required to get the correct answer.
To address the problem, Intel has invented what they call their “Variable Precision Floating Point Unit. The idea here is to build smarts into the hardware such that the computation is confined to the significant digits rather than the programmer-defined value. Intel’s has built an FP unit prototype that automagically right-sizes the floating point computation by using something called certainty tracking to determine the required accuracy.
The prototype has three floating point gears: 24-bit, 12-bit and 6-bit, and uses the certainty tracking to determine which bit width is appropriate. When less digits are warranted, there are fewer bits to shuffle, so not only is energy saved, but performance is increased as well.
Rattner claimed the design is able to cut energy consumption by as much as 50 percent over a conventional FP design. According to Intel, the prototype, which is clocked at 1.45GHz, is able to deliver between 52 and 162 gigaflops/watt. Intel estimates that if they used NTV techniques on their variable precision floating point design, they could realize an additional 7-fold efficiency gain. (For reference, a 20MW exaflop system needs an energy efficiency of just 50 gigaflops/watt, but that includes the entire microprocessor as well as external memory, I/O chips, network fabric, and so on.)
Rattner said the technology is applicable to GPUs (especially for visual computing and traditional graphics) and HPC-type processor designs. In the case of the latter, the implication is that it could be used for Intel’s Many Integrated Core (MIC) processors, which are essentially big floating point processors in an x86 wrapper. In both the graphics and HPC case, the energy efficiency of the floating point hardware is critical to the value proposition of the associated products.
“We have lots of plans for this technology,” said Rattner, “and you can certainly expect to see it as we move out toward the middle of the decade and beyond, where these energy challenges become even more severe than they are today.”