What Knights Landing Is Not

By James Reinders, Intel

June 18, 2016

As we get ready to launch the newest member of the Intel Xeon Phi family, code named Knights Landing, it is natural that there be some questions and potentially some confusion.

I have found that everything is clear, when we really understand that Knights Landing is an Intel processor. That makes it NOT Knights Corner. That makes it NOT a GPU. That makes it NOT a PCIe limited accelerator. That makes it NOT force large, new, and unique investments in software programming.

Perhaps everything is most clear when we discuss what it is and what it is not.

Knights Landing is NOT Knights Corner

Knights Corner, the first Intel Xeon Phi product, was a coprocessor. Knights Corner has been extraordinarily successful powering many of the world’s fastest computers. Nevertheless, Knights Corner required a hot processor, shuffling of data over the PCIe bus, and often the use of offload-style programming due to limited memory capacity and strong Amdahl’s Law effects when running less parallel code.

Knights Landing, as a processor, is a very easy upgrade for a Knights Corner user. Applications that used Knights Corner run even better on Knights Landing. Even bigger news is this: applications which were never able to adapt to the limitations of Knights Corner (or offloading to GPUs for that matter) will find Knights Landing an exciting option.


Knights Landing is NOT a GPU (neither was Knights Corner)

Knights Landing is a full-fledged, highly scalable, Intel processor. This processor can reach unprecedented levels of performance and parallelism, without giving up programmability. You can use the same parallel programming models, the same tools, and the same binaries that run today on other Intel processors.

Programming languages that work for processors, just work for Knights Landing too. Programming models, like OpenMP, MPI and TBB, just work for Knights Landing also.

Restrictive models tailored for GPUs, including kernel programming in CUDA and OpenCL, do not apply to processors (and I’m not talking just about Intel processors). We do not need them, because we have the full richness and portability of processor programming models fully available on Knights Landing.

Knights Landing is NOT going to invalidate prior processor coding efforts

It’s Knights Landing that really brings us home. It’s a full processor from Intel, one that happens to have up to 72 cores. It has an unprecedented ability to perform on highly parallel programs while being compatible with the tools and programming models common to Intel processors.

One of the first things I did when I initially logged on to a Knights Landing machine was to type in “yum install emacs.” I’m sure that whoever built that emacs binary had never heard of Knights Landing. It worked and I was happy to have the power of emacs so as to no be slowed by the primitive “vi.” I am so happy that software just runs, without a recompilation needed. No need to do something weird with Knights Landing to use it with your favorite software. It’s just like any other processor from Intel in that respect! It can run anything you would expect a processor to run: C, C++, Fortran, Python, and much more. It really is a full processor!

We think that parallel programming is challenging enough. That’s why we took a different approach compared to other device designs – especially GPUs. Our goal has been to deliver never before attainable processor performance while remaining compatible with existing software and tools. It’s quite an accomplishment.

Reinders-KNL-FullCover
Front jacket for “Intel Xeon Phi Processor High Performance Programming, Knights Landing Edition” by James Reinders, Jim Jeffers and Avinash Sodani

Knights Landing is NOT inflexible

When we are considering the design for a new computer, we ask a variety of basic questions, consider options, make choices, and bake a set of choices into a design. In the past, when the topic of using high bandwidth memory came up, there as always a debate: should we make it a cache or should we make it a scratchpad memory? And that, of course, depends to a certain extent on whether your application is cache-friendly – and most are – or if it’s one of those apps that is not cache-friendly and you think you can do better with scratch pad memory. Previously, we generally had to design the computer choosing one approach or the other and then live with the decision. With Knights Landing, we offer choices which make Knights Landing amazingly versatile.

Knights Landing integrates high bandwidth memory known as MCDRAM which greatly enhances performance.

Unprecedented configurability allows it to be operated in different “memory modes.” MCDRAM can either be treated as a high bandwidth memory-side cache, or it can be identified as high bandwidth memory, or a little of each. Knights Landing also supports different “cluster modes,” allowing it to behave as a cluster with one, two or four NUMA domains.

Reinders-KNL-Chapter17
Source: “Intel Xeon Phi Processor High Performance Programming, Knights Landing Edition,” 2016; used with permission – click to enlarge

As Jim Jeffers and I say in our book on Knights Landing, “Knights Landing offers an unprecedented variety of configurations which have traditionally been available only as hardwired and unchangeable design decisions. Specifically, the choices realized by the cluster modes and the memory modes. This wide ranging support allows Knights Landing to act like very different machines based on the configuration used to initialize the CPU, the operating system, and then the applications.” This means that Knights Landing can be adapted to fit application needs.

Knights Landing is NOT limited by small memory and offloading

Knights Landing processors support up to 384 GB DDR using 6 channels (~90GBs sustained bandwidth) memory and do not require applying offload constructs to hot spots because an entire application will run on the processor itself.

Reinders-KNL-Chapter22
Source: “Intel Xeon Phi Processor High Performance Programming, Knights Landing Edition,” 2016; used with permission – click to enlarge

Consider the weather forecasting program called WRF (Weather Research and Forecasting). It does not have just a few hot spots where it does all its computations – instead it has a huge number of algorithms used to solve different problems. There are many parts of the application that you would like to run very fast, especially the particularly complex algorithms. Since it all runs on Knights Landing, we’ve seen very nice results, which I have documented in chapter 22 of the new Knights Landing book, coupled with the ease of using the same code as we would on any processor. Programs like this are essentially an insurmountable challenge for a GPU or coprocessor.

Machine learning and data analytics will receive a boost from the introduction of Knights Landing2 . Both tend to apply computational models to large datasets – the constraints have always been the amount of data you can handle given the computational power available to you. Knights Landing is a highly scalable, highly parallel device that is well suited to handle large, complex computations. Because it is a processor rather than a coprocessor, the Intel Xeon Phi technology provides you with more access to your data. Best of all you are working with an on-package, very large processor-sized memory without the limits of any offload device (coprocessor or GPUs).

Reinders-KNL-Chapter24
Source: “Intel Xeon Phi Processor High Performance Programming, Knights Landing Edition,” 2016; used with permission – click to enlarge

The same holds true for visualization applications – Knights Landing provides a new level of flexibility for these kinds of highly specialized, data intensive workloads. Many people are surprised that Knights Landing can consistently beat the leading GPUs in visualization benchmarks 1 . But this is really not surprising when you consider that a GPU has a hard coded graphics pipeline, which is quite inflexible. Knights Landing, being a processor, has none of those constraints. Plus, you don’t wind up shipping massive amounts of data across the PCIe bus; the data is stored in on-package memory and is available for immediate processing.

Moving Toward Exascale

I think we can safely predict a long and happy life for the evolving Intel Xeon Phi processor family, which includes Knights Landing and all its descendants. Odds are that these next generation processors will play a major role in meeting one of HPC’s most exciting grand challenges – the realization of exascale.

Los Alamos National Laboratory’s Trinity supercomputer and the Cori supercomputer from NERSC are pre-exascale systems that will be operational in 2016. Both are powered by Knights Landing and are proof that double-digit petascale performance and the development of exascale machines are attainable without the use of attached accelerators or coprocessors.

And that’s why we emphasize that Knights Landing is a processor – a full-featured, extraordinarily powerful, highly parallel CPU – not a coprocessor or accelerator. It’s a major milestone on the road to exascale and an exciting new era in the world of high performance computing.

1 Intel Xeon Phi Processor High Performance Programming Knights Landing Edition, chapter 17, Software-defined Visualization

2 Intel Xeon Phi Processor High Performance Programming Knights Landing Edition, chapter 24, Machine Learning

All figures are reproduced with permission from Intel Xeon Phi Processor High Performance Programming, Knights Landing Edition by James Reinders, Jim Jeffers and Avinash Sodani, copyright 2016, published by Morgan Kaufmann, ISBN 978-0-12-809194-4. Figures are available for download at http://lotsofcores.com/KNLbook.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Dell’s AMD-Powered Server Line Targets High-End Jobs

September 17, 2019

Dell Technologies rolled out five new servers this week based on AMD’s latest Epyc processor that are geared toward data-driven workloads running on increasingly popular multi-cloud platforms as well as in the HPC data Read more…

By George Leopold

Cerebras to Supply DOE with Wafer-Scale AI Supercomputing Technology

September 17, 2019

Cerebras Systems, which debuted its wafer-scale AI silicon at Hot Chips last month, has entered into a multi-year partnership with Argonne National Laboratory and Lawrence Livermore National Laboratory as part of a larger collaboration with the U.S. Department of Energy... Read more…

By Tiffany Trader

Better Scientific Software: Turn Your Passion into Cash

September 13, 2019

Do you know your way around scientific software and programming? You think you can contribute to the community by making scientific software better? If so, then the Better Scientific Software (BSSW) organization wants yo Read more…

By Dan Olds

AWS Solution Channel

A Guide to Discovering the Best AWS Instances and Configurations for Your HPC Workload

The flexibility and heterogeneity of HPC cloud services provide a welcome contrast to the constraints of on-premises HPC. Every HPC configuration is potentially accessible to any given workload in a well-resourced cloud HPC deployment, with vast scalability to spin up as much compute as that workload demands in any given moment. Read more…

HPE Extreme Performance Solutions

Intel FPGAs: More Than Just an Accelerator Card

FPGA (Field Programmable Gate Array) acceleration cards are not new, as they’ve been commercially available since 1984. Typically, the emphasis around FPGAs has centered on the fact that they’re programmable accelerators, and that they can truly offer workload specific hardware acceleration solutions without requiring custom silicon. Read more…

IBM Accelerated Insights

Rumors of My Death Are Still Exaggerated: The Mainframe

[Connect with Spectrum users and learn new skills in the IBM Spectrum LSF User Community.]

As of 2017, 92 of the world’s top 100 banks used mainframes. Read more…

Google’s ML Compiler Initiative Advances

September 12, 2019

Machine learning models running on everything from cloud platforms to mobile phones are posing new challenges for developers faced with growing tool complexity. Google’s TensorFlow team unveiled an open-source machine Read more…

By George Leopold

Cerebras to Supply DOE with Wafer-Scale AI Supercomputing Technology

September 17, 2019

Cerebras Systems, which debuted its wafer-scale AI silicon at Hot Chips last month, has entered into a multi-year partnership with Argonne National Laboratory and Lawrence Livermore National Laboratory as part of a larger collaboration with the U.S. Department of Energy... Read more…

By Tiffany Trader

IDAS: ‘Automagic’ HPC With Training Wheels

September 12, 2019

High-performance computing (HPC) for research is notorious for having steep barriers to entry. For this reason, high-tech disciplines were early adopters, have Read more…

By Elizabeth Leake

Univa Brings Cloud Automation to Slurm Users with Navops Launch 2.0

September 11, 2019

Univa, the company behind Grid Engine, announced today its HPC cloud-automation platform NavOps Launch will support the popular open-source workload scheduler Slurm. With the release of NavOps Launch 2.0, “Slurm users will have access to the same cloud automation capabilities... Read more…

By Tiffany Trader

When Dense Matrix Representations Beat Sparse

September 9, 2019

In our world filled with unintended consequences, it turns out that saving memory space to help deal with GPU limitations, knowing it introduces performance pen Read more…

By James Reinders

Eyes on the Prize: TACC’s Frontera Quickly Ramps up Science Agenda

September 9, 2019

Announced a year ago and officially launched a week ago, the Texas Advanced Computing Center’s Frontera – now the fastest academic supercomputer (~25 petefl Read more…

By John Russell

Quantum Roundup: IBM Goes to School, Delft Tackles Networking, Rigetti Updates

September 5, 2019

IBM today announced a new open source quantum ‘textbook’, a series of quantum education videos, and plans to expand its nascent quantum hackathon program. L Read more…

By John Russell

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

Fastest Academic Supercomputer Enters Full Production at TACC, Just in Time for Hurricane Season

September 3, 2019

Frontera, the NSF supercomputer installed at the Texas Advanced Computing Center (TACC) in June, passed its formal acceptance last week and is now officially la Read more…

By Tiffany Trader

High Performance (Potato) Chips

May 5, 2006

In this article, we focus on how Procter & Gamble is using high performance computing to create some common, everyday supermarket products. Tom Lange, a 27-year veteran of the company, tells us how P&G models products, processes and production systems for the betterment of consumer package goods. Read more…

By Michael Feldman

Supercomputer-Powered AI Tackles a Key Fusion Energy Challenge

August 7, 2019

Fusion energy is the Holy Grail of the energy world: low-radioactivity, low-waste, zero-carbon, high-output nuclear power that can run on hydrogen or lithium. T Read more…

By Oliver Peckham

AMD Verifies Its Largest 7nm Chip Design in Ten Hours

June 5, 2019

AMD announced last week that its engineers had successfully executed the first physical verification of its largest 7nm chip design – in just ten hours. The AMD Radeon Instinct Vega20 – which boasts 13.2 billion transistors – was tested using a TSMC-certified Calibre nmDRC software platform from Mentor. Read more…

By Oliver Peckham

TSMC and Samsung Moving to 5nm; Whither Moore’s Law?

June 12, 2019

With reports that Taiwan Semiconductor Manufacturing Co. (TMSC) and Samsung are moving quickly to 5nm manufacturing, it’s a good time to again ponder whither goes the venerable Moore’s law. Shrinking feature size has of course been the primary hallmark of achieving Moore’s law... Read more…

By John Russell

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

Cray Wins NNSA-Livermore ‘El Capitan’ Exascale Contract

August 13, 2019

Cray has won the bid to build the first exascale supercomputer for the National Nuclear Security Administration (NNSA) and Lawrence Livermore National Laborator Read more…

By Tiffany Trader

AMD Launches Epyc Rome, First 7nm CPU

August 8, 2019

From a gala event at the Palace of Fine Arts in San Francisco yesterday (Aug. 7), AMD launched its second-generation Epyc Rome x86 chips, based on its 7nm proce Read more…

By Tiffany Trader

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

June 17, 2019

As the Top500 list was being announced at ISC in Frankfurt today with an upgraded petascale Arm supercomputer in the top third of the list, Nvidia announced its Read more…

By Tiffany Trader

Leading Solution Providers

ISC 2019 Virtual Booth Video Tour

CRAY
CRAY
DDN
DDN
DELL EMC
DELL EMC
GOOGLE
GOOGLE
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
VERNE GLOBAL
VERNE GLOBAL

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

Top500 Purely Petaflops; US Maintains Performance Lead

June 17, 2019

With the kick-off of the International Supercomputing Conference (ISC) in Frankfurt this morning, the 53rd Top500 list made its debut, and this one's for petafl Read more…

By Tiffany Trader

A Behind-the-Scenes Look at the Hardware That Powered the Black Hole Image

June 24, 2019

Two months ago, the first-ever image of a black hole took the internet by storm. A team of scientists took years to produce and verify the striking image – an Read more…

By Oliver Peckham

Cray – and the Cray Brand – to Be Positioned at Tip of HPE’s HPC Spear

May 22, 2019

More so than with most acquisitions of this kind, HPE’s purchase of Cray for $1.3 billion, announced last week, seems to have elements of that overused, often Read more…

By Doug Black and Tiffany Trader

Chinese Company Sugon Placed on US ‘Entity List’ After Strong Showing at International Supercomputing Conference

June 26, 2019

After more than a decade of advancing its supercomputing prowess, operating the world’s most powerful supercomputer from June 2013 to June 2018, China is keep Read more…

By Tiffany Trader

Qualcomm Invests in RISC-V Startup SiFive

June 7, 2019

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups. Last fall, Esperanto Technologies announced a $58 million funding round. Read more…

By George Leopold

Intel Confirms Retreat on Omni-Path

August 1, 2019

Intel Corp.’s plans to make a big splash in the network fabric market for linking HPC and other workloads has apparently belly-flopped. The chipmaker confirmed to us the outlines of an earlier report by the website CRN that it has jettisoned plans for a second-generation version of its Omni-Path interconnect... Read more…

By Staff report

Intel Debuts Pohoiki Beach, Its 8M Neuron Neuromorphic Development System

July 17, 2019

Neuromorphic computing has received less fanfare of late than quantum computing whose mystery has captured public attention and which seems to have generated mo Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This