Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

By James Reinders

June 29, 2017

In this contributed feature, James Reinders explores how AVX-512 vector processing will add flexibility to Intel’s forthcoming “Scalable” processors.

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms based on floating point (FP) numbers. Algorithms can definitely benefit from basing their mathematics on bits and integers (bytes, words) if we could just accelerate them too. FPGAs can do this, but the hardware and software costs remain very high. GPUs aren’t designed to operate on non-FP data. Intel AVX introduced some support, and now Intel AVX-512 is bringing a great deal of flexibility to processors. I will share why I’m convinced that the “AVX512VL” capability in particular is a hidden gem that will let AVX-512 be much more useful for compilers and developers alike.

Fortunately for software developers, Intel has done a poor job keeping the “secret” that AVX-512 is coming to Intel’s recently announced Xeon Scalable processor line very soon. Amazon Web Services has publically touted AVX-512 on Skylake as coming soon!

It is timely to examine the new AVX-512 capabilities and their ability to impact beyond the more regular HPC needs for floating point only workloads. The hidden gem in all this, which enables shifting to AVX-512 more easily, is the “VL” (vector length) extensions which allow AVX-512 instructions to behave like SSE or AVX/AVX2 instructions when that suits us. This is a clever and powerful addition to enable its adoption in a wider assortment of software more quickly. The VL extensions mean that programmers (and compilers) do not need to shift immediately from 256-bits (AVX/AVX2) to 512-bits to use the new bit/byte/word manipulations. This transitional benefit is useful not only for an interim, but also for applications which find 256-bits more natural (perhaps a small, but important, subset of problems).

The “future Xeon processor” extensions for AVX-512 were first announced in mid-2014. Intel has done the right things to make software ready for it (for instance we can google for “gcc SKX” – where SKX is widely speculated to be a contraction of “Skylake” and “Xeon”).  For several years now, the gcc, Intel, Microsoft, clang and ispc compilers have supported these instructions. Also, some open source software such as embree and mkl-dnn include support. We can create programs today that use these new instructions, and run them easily using Intel’s Software Development Emulator (SDE). Finally, after years of “leaking via software patches,” in May Intel officially announced that AVX-512 will be in the highly anticipated Skylake/Purley platform as the first processor in the new Intel Xeon Processor Scalable Family (successor to the Xeon E5 and E7 product lines).

Vectorizing more than just Floating Point
The net effect: when Intel Xeon processors support AVX-512 we will have exciting new capabilities that extend the obvious use of AVX-512 for HPC and AI/ML/HPDA workloads to offer flexibility perfect for vectorization needs that include integer and bit-oriented data types as well as the strong floating-point support that first appeared with AVX-512 on Intel Xeon Phi processors. While most HPC and AI/ML/HPDA workloads lean on floating point today, there is plenty of reason to believe that algorithm innovations can benefit from integer and bit-oriented data types when hardware acceleration is available. This makes these AVX-512 developments very exciting!

AVX introduced some bit manipulation and byte/word capabilities. AVX-512 expands greatly on these capabilities. It’s the “VL” (vector length) extensions that ties SSE/AVX/AVX2/AVX_512 together in a clever way that makes these new capabilities easier to adopt, for programmers, tools and compilers.

For those exploring new algorithms for AI, including machine learning and HPDA workloads, the inclusion for bit, byte, and word operations alongside floating point opens up exciting new possibilities. The vector length extensions make them immediately useful to SSE/AVX/AVX2 programmers without forcing an immediate shift to 512-bits.

Three Highlights in the extended AVX-512
Intel documentation and the CPUID enabling bits divide up the “SKX” extensions to into AVX512DQ, AVX512BW, and AVX512VL.

  • AVX512DQ is vector support for Double-word and Quad-word integers, also commonly thought of as int32/int and int64/long. In addition to integer arithmetic and bitwise operations, there are instructions for conversions to/from floating-point vectors. Masking is supported down to the byte level which offers amazing flexibility in using these instructions.
  • AVX512BW is vector support for Byte (half-words) and Words, also commonly thought of as char/int8 and short/int16. A rich set of instructions for integer arithmetic and bitwise operations are offered. Masking is supported down to the byte level with AVX512BW as well.
  • AVX512VL ups the ante enormously, by making almost all of the AVX512 instructions available as SSE and AVX instructions, but with a full 32 register capability (at least double the registers that SSE or AVX instructions have to offer). AVX512VL is not actually a set of new instructions. It is an orthogonal feature that applies to nearly all AVX-512 instructions (the exceptions make sense – a few AVX512F and AVX512DQ instructions with implicit 256 or 128 bit widths such as those explicitly working on 32×4 and 64×2 data).

The trend with vector instructions to grow to longer and longer lengths has not been without its disadvantages and difficulties for programmers. While longer vectors are often a great thing for many supercomputer applications, longer vector lengths are often more difficult to use all the time when handling compute problems that do not always have long vectors to process. The VL extensions to AVX-512 bring flexibility to Intel’s AVX-512 that broaden its applicability.

AVX-512 instructions offer a rich collection of operations but they have always operated on the 512-bit registers (ZMM). The downside of a 512-bit register is that it wastes bandwidth and power to use a 512-bit instructions and registers for 256 or 128-bit operations.  Well optimized code (such as that emitted by compilers, or experienced intrinsic or assembly programmers) would seemingly have a careful mix of SSE (128-bit SIMD) and AVX (256-bit SIMD). Doing this is clumsy at best, and complicated by a performance penalty when mixing SSE and AVX code (fortunately there is no performance penalty when mixing AVX and AVX-512 instructions).

The VL extension enables AVX-512 instructions to operate on XMM (128-bit) and YMM (256-bit) registers, and are not limited to just the full ZMM registers. This symmetry definitely is good news. AVX-512, with the VL extension, seems well set to be the programming option of choice for compilers and hand coders because it unifies so many capabilities together along with access to 32 vector registers regardless of their size (XMM, YMM or ZMM).

More AVX-512 features after Skylake?
There is further evidence in the open source enabling work of additional instructions coming after Skylake. Intel has placed documentation of these into its Software Developer Guides, and helped add support to open source projects. Again, this is all good news for software developer because it means software tools do not need to lag the hardware. The four categories of instructions that are documented by Intel thus far, and are not enabled by compiler options for “KNL” (Intel Xeon Phi processors) or “SKX” (Skylake Xeon processors) are:

  • AVX512IFMA: 2 instructions for high/low result of Fused Multiply-Add for 2/4/8-element vectors of 52-bit integers stored in 64-bit fields of 128/256/512-bit vectors.
  • AVX512VBMI: Byte-level vector permute (on 128/256/512/1024-bit vectors) and a select+pack instruction — 4 instructions (with multiple argument types)
  • AVX512_4VNNIW: Vector instructions for deep learning enhanced word variable precision.
  • AVX512_4FMAPS: Vector instructions for deep learning floating-point single precision.

Speculation, supported by open source documentation, says that the first two will appear in a Xeon processor after Skylake, and the latter two will appear in a future Intel Xeon Phi processor (Knights Mill is commonly suggested).

Summary
Regardless of how perfect my speculations are on timing, it is clear that Intel is investing heavily in their expansion of vector capabilities to much more than floating-point operations.  This gives a much-expanded capability for algorithms to be developed with a much wider variety of arithmetic and bitwise operations than floating-point alone can offer.  Who will take advantage of these remains to be seen – but ML/AI and cryptographic programmers seem to be obvious candidates.

With Skylake-architecture based Intel Xeon processors coming soon, it is a great time for programmers to take a closer look.  The instructions are already well supported in tools, and the Intel Software Development Emulator (SDE) makes it easy to run the instructions today.

For More Information
I recommend the following sites for more detailed information:

  • Intel’s online guide to AVX-512 instructions as they are best accessed in C/C++ (intrinsics) has a detailed guide (click on instructions to expand) for AVX-512 instructions.
  • The Intel Software Development Emulator (SDE) allows us to run programs using these Intel AVX-512 instructions on our current x86 systems. The SDE runs code via emulation, which is accurate but slower than on hardware with support for the instructions built-in.
  • Intel documentation is massive, a complete list “Intel® 64 and IA-32 Architectures Software Developer Manuals” covers everything, the specific documents to learn about AVX-512VL are the “Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4” and “Intel® architecture instruction set extensions programming reference.” Normally, information in the latter document migrates to the former when support appears in a shipping product – so eventually everything about VL will be in the first document. I did not link the specific documents because their links change. We can find them on the main documentation page and click there to get the latest documents. I scroll through them by searching for “AVX512VL” in my PDF viewer and moving from match to match.

About the Author
James Reinders likes fast computers and the software tools to make them speedy. Last year, James concluded a 10,001 day career at Intel where he contributed to projects including the world’s first TeraFLOPS supercomputer (ASCI Red), compilers and architecture work for a number of Intel processors and parallel systems. James is the founding editor of The Parallel Universe magazine and has been the driving force behind books on VTune (2005), TBB (2007), Structured Parallel Programming (2012), Intel Xeon Phi coprocessor programming (2013), Multithreading for Visual Effects (2014), High Performance Parallelism Pearls Volume One (2014) and Volume Two (2015), and Intel Xeon Phi processor (2016). James resides in Oregon, where he enjoys both gardening and HPC and HPDA consulting.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

Russian and American Scientists Achieve 50% Increase in Data Transmission Speed

September 20, 2018

As high-performance computing becomes increasingly data-intensive and the demand for shorter turnaround times grows, data transfer speed becomes an ever more important bottleneck. Now, in an article published in IEEE Tra Read more…

By Oliver Peckham

IBM to Brand Rescale’s HPC-in-Cloud Platform

September 20, 2018

HPC (or big compute)-in-the-cloud platform provider Rescale has formalized the work it’s been doing in partnership with public cloud vendors by announcing its Powered by Rescale program – with IBM as its first named Read more…

By Doug Black

Democratization of HPC Part 1: Simulation Sheds Light on Building Dispute

September 20, 2018

This is the first of three articles demonstrating the growing acceptance of High Performance Computing especially in new user communities and application areas. Major reasons for this trend are the ongoing improvements i Read more…

By Wolfgang Gentzsch

HPE Extreme Performance Solutions

Introducing the First Integrated System Management Software for HPC Clusters from HPE

How do you manage your complex, growing cluster environments? Answer that big challenge with the new HPC cluster management solution: HPE Performance Cluster Manager. Read more…

IBM Accelerated Insights

Clouds Over the Ocean – a Healthcare Perspective

Advances in precision medicine, genomics, and imaging; the widespread adoption of electronic health records; and the proliferation of medical Internet of Things (IoT) and mobile devices are resulting in an explosion of structured and unstructured healthcare-related data. Read more…

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Gordon Bell Prize used Summit in their work. That’s impres Read more…

By John Russell

Summit Supercomputer is Already Making its Mark on Science

September 20, 2018

Summit, now the fastest supercomputer in the world, is quickly making its mark in science – five of the six finalists just announced for the prestigious 2018 Read more…

By John Russell

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Nvidia Accelerates AI Inference in the Datacenter with T4 GPU

September 14, 2018

Nvidia is upping its game for AI inference in the datacenter with a new platform consisting of an inference accelerator chip--the new Turing-based Tesla T4 GPU- Read more…

By George Leopold

DeepSense Combines HPC and AI to Bolster Canada’s Ocean Economy

September 13, 2018

We often hear scientists say that we know less than 10 percent of the life of the oceans. This week, IBM and a group of Canadian industry and government partner Read more…

By Tiffany Trader

Rigetti (and Others) Pursuit of Quantum Advantage

September 11, 2018

Remember ‘quantum supremacy’, the much-touted but little-loved idea that the age of quantum computing would be signaled when quantum computers could tackle Read more…

By John Russell

How FPGAs Accelerate Financial Services Workloads

September 11, 2018

While FSI companies are unlikely, for competitive reasons, to disclose their FPGA strategies, James Reinders offers insights into the case for FPGAs as accelerators for FSI by discussing performance, power, size, latency, jitter and inline processing. Read more…

By James Reinders

Update from Gregory Kurtzer on Singularity’s Push into FS and the Enterprise

September 11, 2018

Container technology is hardly new but it has undergone rapid evolution in the HPC space in recent years to accommodate traditional science workloads and HPC systems requirements. While Docker containers continue to dominate in the enterprise, other variants are becoming important and one alternative with distinctly HPC roots – Singularity – is making an enterprise push targeting advanced scale workload inclusive of HPC. Read more…

By John Russell

At HPC on Wall Street: AI-as-a-Service Accelerates AI Journeys

September 10, 2018

AIaaS – artificial intelligence-as-a-service – is the technology discipline that eases enterprise entry into the mysteries of the AI journey while lowering Read more…

By Doug Black

TACC Wins Next NSF-funded Major Supercomputer

July 30, 2018

The Texas Advanced Computing Center (TACC) has won the next NSF-funded big supercomputer beating out rivals including the National Center for Supercomputing Ap Read more…

By John Russell

IBM at Hot Chips: What’s Next for Power

August 23, 2018

With processor, memory and networking technologies all racing to fill in for an ailing Moore’s law, the era of the heterogeneous datacenter is well underway, Read more…

By Tiffany Trader

Requiem for a Phi: Knights Landing Discontinued

July 25, 2018

On Monday, Intel made public its end of life strategy for the Knights Landing "KNL" Phi product set. The announcement makes official what has already been wide Read more…

By Tiffany Trader

CERN Project Sees Orders-of-Magnitude Speedup with AI Approach

August 14, 2018

An award-winning effort at CERN has demonstrated potential to significantly change how the physics based modeling and simulation communities view machine learni Read more…

By Rob Farber

ORNL Summit Supercomputer Is Officially Here

June 8, 2018

Oak Ridge National Laboratory (ORNL) together with IBM and Nvidia celebrated the official unveiling of the Department of Energy (DOE) Summit supercomputer toda Read more…

By Tiffany Trader

New Deep Learning Algorithm Solves Rubik’s Cube

July 25, 2018

Solving (and attempting to solve) Rubik’s Cube has delighted millions of puzzle lovers since 1974 when the cube was invented by Hungarian sculptor and archite Read more…

By John Russell

AMD’s EPYC Road to Redemption in Six Slides

June 21, 2018

A year ago AMD returned to the server market with its EPYC processor line. The earth didn’t tremble but folks took notice. People remember the Opteron fondly Read more…

By John Russell

House Passes $1.275B National Quantum Initiative

September 17, 2018

Last Thursday the U.S. House of Representatives passed the National Quantum Initiative Act (NQIA) intended to accelerate quantum computing research and developm Read more…

By John Russell

Leading Solution Providers

SC17 Booth Video Tours Playlist

Altair @ SC17

Altair

AMD @ SC17

AMD

ASRock Rack @ SC17

ASRock Rack

CEJN @ SC17

CEJN

DDN Storage @ SC17

DDN Storage

Huawei @ SC17

Huawei

IBM @ SC17

IBM

IBM Power Systems @ SC17

IBM Power Systems

Intel @ SC17

Intel

Lenovo @ SC17

Lenovo

Mellanox Technologies @ SC17

Mellanox Technologies

Microsoft @ SC17

Microsoft

Penguin Computing @ SC17

Penguin Computing

Pure Storage @ SC17

Pure Storage

Supericro @ SC17

Supericro

Tyan @ SC17

Tyan

Univa @ SC17

Univa

Sandia to Take Delivery of World’s Largest Arm System

June 18, 2018

While the enterprise remains circumspect on prospects for Arm servers in the datacenter, the leadership HPC community is taking a bolder, brighter view of the x86 server CPU alternative. Amongst current and planned Arm HPC installations – i.e., the innovative Mont-Blanc project, led by Bull/Atos, the 'Isambard’ Cray XC50 going into the University of Bristol, and commitments from both Japan and France among others -- HPE is announcing that it will be supply the United States National Nuclear Security Administration (NNSA) with a 2.3 petaflops peak Arm-based system, named Astra. Read more…

By Tiffany Trader

MLPerf – Will New Machine Learning Benchmark Help Propel AI Forward?

May 2, 2018

Let the AI benchmarking wars begin. Today, a diverse group from academia and industry – Google, Baidu, Intel, AMD, Harvard, and Stanford among them – releas Read more…

By John Russell

D-Wave Breaks New Ground in Quantum Simulation

July 16, 2018

Last Friday D-Wave scientists and colleagues published work in Science which they say represents the first fulfillment of Richard Feynman’s 1982 notion that Read more…

By John Russell

Intel Pledges First Commercial Nervana Product ‘Spring Crest’ in 2019

May 24, 2018

At its AI developer conference in San Francisco yesterday, Intel embraced a holistic approach to AI and showed off a broad AI portfolio that includes Xeon processors, Movidius technologies, FPGAs and Intel’s Nervana Neural Network Processors (NNPs), based on the technology it acquired in 2016. Read more…

By Tiffany Trader

TACC’s ‘Frontera’ Supercomputer Expands Horizon for Extreme-Scale Science

August 29, 2018

The National Science Foundation and the Texas Advanced Computing Center announced today that a new system, called Frontera, will overtake Stampede 2 as the fast Read more…

By Tiffany Trader

Intel Announces Cooper Lake, Advances AI Strategy

August 9, 2018

Intel's chief datacenter exec Navin Shenoy kicked off the company's Data-Centric Innovation Summit Wednesday, the day-long program devoted to Intel's datacenter Read more…

By Tiffany Trader

GPUs Power Five of World’s Top Seven Supercomputers

June 25, 2018

The top 10 echelon of the newly minted Top500 list boasts three powerful new systems with one common engine: the Nvidia Volta V100 general-purpose graphics proc Read more…

By Tiffany Trader

The Machine Learning Hype Cycle and HPC

June 14, 2018

Like many other HPC professionals I’m following the hype cycle around machine learning/deep learning with interest. I subscribe to the view that we’re probably approaching the ‘peak of inflated expectation’ but not quite yet starting the descent into the ‘trough of disillusionment. This still raises the probability that... Read more…

By Dairsie Latimer

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This