Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors

By James Reinders

June 29, 2017

In this contributed feature, James Reinders explores how AVX-512 vector processing will add flexibility to Intel’s forthcoming “Scalable” processors.

Imagine if we could use vector processing on something other than just floating point problems.  Today, GPUs and CPUs work tirelessly to accelerate algorithms based on floating point (FP) numbers. Algorithms can definitely benefit from basing their mathematics on bits and integers (bytes, words) if we could just accelerate them too. FPGAs can do this, but the hardware and software costs remain very high. GPUs aren’t designed to operate on non-FP data. Intel AVX introduced some support, and now Intel AVX-512 is bringing a great deal of flexibility to processors. I will share why I’m convinced that the “AVX512VL” capability in particular is a hidden gem that will let AVX-512 be much more useful for compilers and developers alike.

Fortunately for software developers, Intel has done a poor job keeping the “secret” that AVX-512 is coming to Intel’s recently announced Xeon Scalable processor line very soon. Amazon Web Services has publically touted AVX-512 on Skylake as coming soon!

It is timely to examine the new AVX-512 capabilities and their ability to impact beyond the more regular HPC needs for floating point only workloads. The hidden gem in all this, which enables shifting to AVX-512 more easily, is the “VL” (vector length) extensions which allow AVX-512 instructions to behave like SSE or AVX/AVX2 instructions when that suits us. This is a clever and powerful addition to enable its adoption in a wider assortment of software more quickly. The VL extensions mean that programmers (and compilers) do not need to shift immediately from 256-bits (AVX/AVX2) to 512-bits to use the new bit/byte/word manipulations. This transitional benefit is useful not only for an interim, but also for applications which find 256-bits more natural (perhaps a small, but important, subset of problems).

The “future Xeon processor” extensions for AVX-512 were first announced in mid-2014. Intel has done the right things to make software ready for it (for instance we can google for “gcc SKX” – where SKX is widely speculated to be a contraction of “Skylake” and “Xeon”).  For several years now, the gcc, Intel, Microsoft, clang and ispc compilers have supported these instructions. Also, some open source software such as embree and mkl-dnn include support. We can create programs today that use these new instructions, and run them easily using Intel’s Software Development Emulator (SDE). Finally, after years of “leaking via software patches,” in May Intel officially announced that AVX-512 will be in the highly anticipated Skylake/Purley platform as the first processor in the new Intel Xeon Processor Scalable Family (successor to the Xeon E5 and E7 product lines).

Vectorizing more than just Floating Point
The net effect: when Intel Xeon processors support AVX-512 we will have exciting new capabilities that extend the obvious use of AVX-512 for HPC and AI/ML/HPDA workloads to offer flexibility perfect for vectorization needs that include integer and bit-oriented data types as well as the strong floating-point support that first appeared with AVX-512 on Intel Xeon Phi processors. While most HPC and AI/ML/HPDA workloads lean on floating point today, there is plenty of reason to believe that algorithm innovations can benefit from integer and bit-oriented data types when hardware acceleration is available. This makes these AVX-512 developments very exciting!

AVX introduced some bit manipulation and byte/word capabilities. AVX-512 expands greatly on these capabilities. It’s the “VL” (vector length) extensions that ties SSE/AVX/AVX2/AVX_512 together in a clever way that makes these new capabilities easier to adopt, for programmers, tools and compilers.

For those exploring new algorithms for AI, including machine learning and HPDA workloads, the inclusion for bit, byte, and word operations alongside floating point opens up exciting new possibilities. The vector length extensions make them immediately useful to SSE/AVX/AVX2 programmers without forcing an immediate shift to 512-bits.

Three Highlights in the extended AVX-512
Intel documentation and the CPUID enabling bits divide up the “SKX” extensions to into AVX512DQ, AVX512BW, and AVX512VL.

  • AVX512DQ is vector support for Double-word and Quad-word integers, also commonly thought of as int32/int and int64/long. In addition to integer arithmetic and bitwise operations, there are instructions for conversions to/from floating-point vectors. Masking is supported down to the byte level which offers amazing flexibility in using these instructions.
  • AVX512BW is vector support for Byte (half-words) and Words, also commonly thought of as char/int8 and short/int16. A rich set of instructions for integer arithmetic and bitwise operations are offered. Masking is supported down to the byte level with AVX512BW as well.
  • AVX512VL ups the ante enormously, by making almost all of the AVX512 instructions available as SSE and AVX instructions, but with a full 32 register capability (at least double the registers that SSE or AVX instructions have to offer). AVX512VL is not actually a set of new instructions. It is an orthogonal feature that applies to nearly all AVX-512 instructions (the exceptions make sense – a few AVX512F and AVX512DQ instructions with implicit 256 or 128 bit widths such as those explicitly working on 32×4 and 64×2 data).

The trend with vector instructions to grow to longer and longer lengths has not been without its disadvantages and difficulties for programmers. While longer vectors are often a great thing for many supercomputer applications, longer vector lengths are often more difficult to use all the time when handling compute problems that do not always have long vectors to process. The VL extensions to AVX-512 bring flexibility to Intel’s AVX-512 that broaden its applicability.

AVX-512 instructions offer a rich collection of operations but they have always operated on the 512-bit registers (ZMM). The downside of a 512-bit register is that it wastes bandwidth and power to use a 512-bit instructions and registers for 256 or 128-bit operations.  Well optimized code (such as that emitted by compilers, or experienced intrinsic or assembly programmers) would seemingly have a careful mix of SSE (128-bit SIMD) and AVX (256-bit SIMD). Doing this is clumsy at best, and complicated by a performance penalty when mixing SSE and AVX code (fortunately there is no performance penalty when mixing AVX and AVX-512 instructions).

The VL extension enables AVX-512 instructions to operate on XMM (128-bit) and YMM (256-bit) registers, and are not limited to just the full ZMM registers. This symmetry definitely is good news. AVX-512, with the VL extension, seems well set to be the programming option of choice for compilers and hand coders because it unifies so many capabilities together along with access to 32 vector registers regardless of their size (XMM, YMM or ZMM).

More AVX-512 features after Skylake?
There is further evidence in the open source enabling work of additional instructions coming after Skylake. Intel has placed documentation of these into its Software Developer Guides, and helped add support to open source projects. Again, this is all good news for software developer because it means software tools do not need to lag the hardware. The four categories of instructions that are documented by Intel thus far, and are not enabled by compiler options for “KNL” (Intel Xeon Phi processors) or “SKX” (Skylake Xeon processors) are:

  • AVX512IFMA: 2 instructions for high/low result of Fused Multiply-Add for 2/4/8-element vectors of 52-bit integers stored in 64-bit fields of 128/256/512-bit vectors.
  • AVX512VBMI: Byte-level vector permute (on 128/256/512/1024-bit vectors) and a select+pack instruction — 4 instructions (with multiple argument types)
  • AVX512_4VNNIW: Vector instructions for deep learning enhanced word variable precision.
  • AVX512_4FMAPS: Vector instructions for deep learning floating-point single precision.

Speculation, supported by open source documentation, says that the first two will appear in a Xeon processor after Skylake, and the latter two will appear in a future Intel Xeon Phi processor (Knights Mill is commonly suggested).

Summary
Regardless of how perfect my speculations are on timing, it is clear that Intel is investing heavily in their expansion of vector capabilities to much more than floating-point operations.  This gives a much-expanded capability for algorithms to be developed with a much wider variety of arithmetic and bitwise operations than floating-point alone can offer.  Who will take advantage of these remains to be seen – but ML/AI and cryptographic programmers seem to be obvious candidates.

With Skylake-architecture based Intel Xeon processors coming soon, it is a great time for programmers to take a closer look.  The instructions are already well supported in tools, and the Intel Software Development Emulator (SDE) makes it easy to run the instructions today.

For More Information
I recommend the following sites for more detailed information:

  • Intel’s online guide to AVX-512 instructions as they are best accessed in C/C++ (intrinsics) has a detailed guide (click on instructions to expand) for AVX-512 instructions.
  • The Intel Software Development Emulator (SDE) allows us to run programs using these Intel AVX-512 instructions on our current x86 systems. The SDE runs code via emulation, which is accurate but slower than on hardware with support for the instructions built-in.
  • Intel documentation is massive, a complete list “Intel® 64 and IA-32 Architectures Software Developer Manuals” covers everything, the specific documents to learn about AVX-512VL are the “Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4” and “Intel® architecture instruction set extensions programming reference.” Normally, information in the latter document migrates to the former when support appears in a shipping product – so eventually everything about VL will be in the first document. I did not link the specific documents because their links change. We can find them on the main documentation page and click there to get the latest documents. I scroll through them by searching for “AVX512VL” in my PDF viewer and moving from match to match.

About the Author
James Reinders likes fast computers and the software tools to make them speedy. Last year, James concluded a 10,001 day career at Intel where he contributed to projects including the world’s first TeraFLOPS supercomputer (ASCI Red), compilers and architecture work for a number of Intel processors and parallel systems. James is the founding editor of The Parallel Universe magazine and has been the driving force behind books on VTune (2005), TBB (2007), Structured Parallel Programming (2012), Intel Xeon Phi coprocessor programming (2013), Multithreading for Visual Effects (2014), High Performance Parallelism Pearls Volume One (2014) and Volume Two (2015), and Intel Xeon Phi processor (2016). James resides in Oregon, where he enjoys both gardening and HPC and HPDA consulting.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

GTC 2019: Chief Scientist Bill Dally Provides Glimpse into Nvidia Research Engine

March 22, 2019

Amid the frenzy of GTC this week – Nvidia’s annual conference showcasing all things GPU (and now AI) – William Dally, chief scientist and SVP of research, provided a brief but insightful portrait of Nvidia’s rese Read more…

By John Russell

ORNL Helps Identify Challenges of Extremely Heterogeneous Architectures

March 21, 2019

Exponential growth in classical computing over the last two decades has produced hardware and software that support lightning-fast processing speeds, but advancements are topping out as computing architectures reach thei Read more…

By Laurie Varma

Interview with 2019 Person to Watch Jim Keller

March 21, 2019

On the heels of Intel's reaffirmation that it will deliver the first U.S. exascale computer in 2021, which will feature the company's new Intel Xe architecture, we bring you our interview with our 2019 Person to Watch Jim Keller, head of the Silicon Engineering Group at Intel. Read more…

By HPCwire Editorial Team

HPE Extreme Performance Solutions

HPE and Intel® Omni-Path Architecture: How to Power a Cloud

Learn how HPE and Intel® Omni-Path Architecture provide critical infrastructure for leading Nordic HPC provider’s HPCFLOW cloud service.

powercloud_blog.jpgFor decades, HPE has been at the forefront of high-performance computing, and we’ve powered some of the fastest and most robust supercomputers in the world. Read more…

IBM Accelerated Insights

Insurance: Where’s the Risk?

Insurers are facing extreme competitive challenges in their core businesses. Property and Casualty (P&C) and Life and Health (L&H) firms alike are highly impacted by the ongoing globalization, increasing regulation, and digital transformation of their client bases. Read more…

What’s New in HPC Research: TensorFlow, Buddy Compression, Intel Optane & More

March 20, 2019

In this bimonthly feature, HPCwire highlights newly published research in the high-performance computing community and related domains. From parallel programming to exascale to quantum computing, the details are here. Read more…

By Oliver Peckham

GTC 2019: Chief Scientist Bill Dally Provides Glimpse into Nvidia Research Engine

March 22, 2019

Amid the frenzy of GTC this week – Nvidia’s annual conference showcasing all things GPU (and now AI) – William Dally, chief scientist and SVP of research, Read more…

By John Russell

At GTC: Nvidia Expands Scope of Its AI and Datacenter Ecosystem

March 19, 2019

In the high-stakes race to provide the AI life-cycle solution of choice, three of the biggest horses in the field are IBM, Intel and Nvidia. While the latter is only a fraction of the size of its two bigger rivals, and has been in business for only a fraction of the time, Nvidia continues to impress with an expanding array of new GPU-based hardware, software, robotics, partnerships and... Read more…

By Doug Black

Nvidia Debuts Clara AI Toolkit with Pre-Trained Models for Radiology Use

March 19, 2019

AI’s push into healthcare got a boost yesterday with Nvidia’s release of the Clara Deploy AI toolkit which includes 13 pre-trained models for use in radiolo Read more…

By John Russell

It’s Official: Aurora on Track to Be First US Exascale Computer in 2021

March 18, 2019

The U.S. Department of Energy along with Intel and Cray confirmed today that an Intel/Cray supercomputer, "Aurora," capable of sustained performance of one exaf Read more…

By Tiffany Trader

Why Nvidia Bought Mellanox: ‘Future Datacenters Will Be…Like High Performance Computers’

March 14, 2019

“Future datacenters of all kinds will be built like high performance computers,” said Nvidia CEO Jensen Huang during a phone briefing on Monday after Nvidia revealed scooping up the high performance networking company Mellanox for $6.9 billion. Read more…

By Tiffany Trader

Oil and Gas Supercloud Clears Out Remaining Knights Landing Inventory: All 38,000 Wafers

March 13, 2019

The McCloud HPC service being built by Australia’s DownUnder GeoSolutions (DUG) outside Houston is set to become the largest oil and gas cloud in the world th Read more…

By Tiffany Trader

Quick Take: Trump’s 2020 Budget Spares DoE-funded HPC but Slams NSF and NIH

March 12, 2019

U.S. President Donald Trump’s 2020 budget request, released yesterday, proposes deep cuts in many science programs but seems to spare HPC funding by the Depar Read more…

By John Russell

Nvidia Wins Mellanox Stakes for $6.9 Billion

March 11, 2019

The long-rumored acquisition of Mellanox came to fruition this morning with GPU chipmaker Nvidia’s announcement that it has purchased the high-performance net Read more…

By Doug Black

Quantum Computing Will Never Work

November 27, 2018

Amid the gush of money and enthusiastic predictions being thrown at quantum computing comes a proposed cold shower in the form of an essay by physicist Mikhail Read more…

By John Russell

The Case Against ‘The Case Against Quantum Computing’

January 9, 2019

It’s not easy to be a physicist. Richard Feynman (basically the Jimi Hendrix of physicists) once said: “The first principle is that you must not fool yourse Read more…

By Ben Criger

ClusterVision in Bankruptcy, Fate Uncertain

February 13, 2019

ClusterVision, European HPC specialists that have built and installed over 20 Top500-ranked systems in their nearly 17-year history, appear to be in the midst o Read more…

By Tiffany Trader

Why Nvidia Bought Mellanox: ‘Future Datacenters Will Be…Like High Performance Computers’

March 14, 2019

“Future datacenters of all kinds will be built like high performance computers,” said Nvidia CEO Jensen Huang during a phone briefing on Monday after Nvidia revealed scooping up the high performance networking company Mellanox for $6.9 billion. Read more…

By Tiffany Trader

Intel Reportedly in $6B Bid for Mellanox

January 30, 2019

The latest rumors and reports around an acquisition of Mellanox focus on Intel, which has reportedly offered a $6 billion bid for the high performance interconn Read more…

By Doug Black

Looking for Light Reading? NSF-backed ‘Comic Books’ Tackle Quantum Computing

January 28, 2019

Still baffled by quantum computing? How about turning to comic books (graphic novels for the well-read among you) for some clarity and a little humor on QC. The Read more…

By John Russell

Contract Signed for New Finnish Supercomputer

December 13, 2018

After the official contract signing yesterday, configuration details were made public for the new BullSequana system that the Finnish IT Center for Science (CSC Read more…

By Tiffany Trader

It’s Official: Aurora on Track to Be First US Exascale Computer in 2021

March 18, 2019

The U.S. Department of Energy along with Intel and Cray confirmed today that an Intel/Cray supercomputer, "Aurora," capable of sustained performance of one exaf Read more…

By Tiffany Trader

Leading Solution Providers

SC 18 Virtual Booth Video Tour

Advania @ SC18 AMD @ SC18
ASRock Rack @ SC18
DDN Storage @ SC18
HPE @ SC18
IBM @ SC18
Lenovo @ SC18 Mellanox Technologies @ SC18
NVIDIA @ SC18
One Stop Systems @ SC18
Oracle @ SC18 Panasas @ SC18
Supermicro @ SC18 SUSE @ SC18 TYAN @ SC18
Verne Global @ SC18

Deep500: ETH Researchers Introduce New Deep Learning Benchmark for HPC

February 5, 2019

ETH researchers have developed a new deep learning benchmarking environment – Deep500 – they say is “the first distributed and reproducible benchmarking s Read more…

By John Russell

IBM Quantum Update: Q System One Launch, New Collaborators, and QC Center Plans

January 10, 2019

IBM made three significant quantum computing announcements at CES this week. One was introduction of IBM Q System One; it’s really the integration of IBM’s Read more…

By John Russell

IBM Bets $2B Seeking 1000X AI Hardware Performance Boost

February 7, 2019

For now, AI systems are mostly machine learning-based and “narrow” – powerful as they are by today's standards, they're limited to performing a few, narro Read more…

By Doug Black

The Deep500 – Researchers Tackle an HPC Benchmark for Deep Learning

January 7, 2019

How do you know if an HPC system, particularly a larger-scale system, is well-suited for deep learning workloads? Today, that’s not an easy question to answer Read more…

By John Russell

HPC Reflections and (Mostly Hopeful) Predictions

December 19, 2018

So much ‘spaghetti’ gets tossed on walls by the technology community (vendors and researchers) to see what sticks that it is often difficult to peer through Read more…

By John Russell

Arm Unveils Neoverse N1 Platform with up to 128-Cores

February 20, 2019

Following on its Neoverse roadmap announcement last October, Arm today revealed its next-gen Neoverse microarchitecture with compute and throughput-optimized si Read more…

By Tiffany Trader

Move Over Lustre & Spectrum Scale – Here Comes BeeGFS?

November 26, 2018

Is BeeGFS – the parallel file system with European roots – on a path to compete with Lustre and Spectrum Scale worldwide in HPC environments? Frank Herold Read more…

By John Russell

France to Deploy AI-Focused Supercomputer: Jean Zay

January 22, 2019

HPE announced today that it won the contract to build a supercomputer that will drive France’s AI and HPC efforts. The computer will be part of GENCI, the Fre Read more…

By Tiffany Trader

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This