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Tag: DARPA

DARPA Targets Autocomplete for Programmers

Nov 6, 2014 |

If Rice University computer scientists have their way, writing computer software could become as easy as searching the Internet. Two dozen computer scientists from Rice, the University of Texas-Austin, the University of Wisconsin-Madison and the company GrammaTech have joined forces to turn this promise into a reality. With $11 million in DARPA-funding, the group will Read more…

Brainy IBM Chip Packs One Million Neuron Punch

Aug 7, 2014 |

IBM researchers have developed a super-efficient chip inspired by the functioning of the human brain. Named TrueNorth, the chip features 5.4 billion transistors arranged in a network of 4,096 neurosynaptic cores, yielding the equivalent of one million neurons and 256 million synapses. Despite being one of the largest CMOS chips ever built, TrueNorth consumes just 70mW during Read more…

Planning for Post Moore’s Law

May 28, 2014 |

In this video from Hot Chips 25, Dr. Robert Colwell of DARPA delivers an insightful overview on the “looming issue” that is the death of Moore’s law. Colwell starts out with the humorous point that “physics doesn’t care what we believe.” Believing that Moore’s law – Gordon Moore’s 1965 observation that a chip’s transistor count doubles Read more…

Moore’s Law We Miss You Already

Aug 29, 2013 |

As transistors reach the limits of miniaturization, it is only a matter of time until Moore’s Law runs out of steam. The latest expert to weigh-in says Moore’s Law will expire in 2020 at the 7nm node.

STARnet Alliance Seeks Revolution in Chip Design

Jan 23, 2013 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/STARnet_logo_120x.jpg” alt=”” width=”94″ height=”116″ />The Defense Advanced Research Projects Agency (DARPA) and the Semiconductor Research Corporation (SRC) have launched a new consortium to advance the pace of semiconductor innovation in the US as the technology approaches the limits of miniaturization. The main thrust of the project is the creation of the Semiconductor Technology Advanced Research Network, aka STARnet.

Cray Launches Cascade, Embraces Intel-Based Supercomputing

Nov 8, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/Cray_XC30_small.jpg” alt=”” width=”95″ height=”86″ />AMD-loving Cray has launched the XC30 supercomputer, a product line that will be powered by Intel Xeon processors. The platform is based on the company’s “Cascade” architecture, which is designed to bring a variety of processors and coprocessors under a common infrastructure. XC will become Cray’s flagship computing platform as it phases out its XE and XK line over the next year or so.

Oracle Ditches Supercomputing Language Project

Jul 24, 2012 |

Fortress programming language gets axed by Ellison and company.

NERSC Signs Up for Multi-Petaflop “Cascade” Supercomputer

Jul 3, 2012 |

<img style=”float: left;” src=”http://media2.hpcwire.com/hpcwire/NERSC_logo_small.png” alt=”” width=”118″ height=”37″ />The US Department of Energy’s National Energy Research Scientific Computing Center (NERSC) has ordered a two-petaflop “Cascade” supercomputer, Cray’s next-generation HPC platform. The DOE is shelling out $40 million dollars for the system, including about 6.5 petabytes of the company’s Sonexion storage. Installation is scheduled for sometime in 2013.

UHPC Developments Move DARPA Closer to Goals

Aug 30, 2011 |

The Ubiquitous High Performance Computing initiative from DARPA is sparking a rethink of data movement efficiency.

Debt Deal Casts Shadow on US Research Funding

Aug 4, 2011 |

Federal R&D money could be an easy target for cost-cutting with latest legislation.

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