The opening address of the Supercomputing Conference had a surreal quality to it in more ways than one. Between talking avatars, physics-simulated sound, and a Larrabee demo running HPC-type codes, it was hard to separate reality from fantasy.
On Tuesday morning, Intel CTO and HPC aficionado Justin Rattner presented his vision of the future of high performance computing to the SC09 crowd in attendance. Rattner’s thesis: the 3D Web will be the technology driver that revitalizes the HPC business model. More precisely, the combination of HPC and cloud computing will make the 3D Web possible, and, more important to Intel’s bottom line, ubiquitous. “There is nothing more important to the long-term health of the HPC industry than the 3D Web,” said Rattner.
Why does high performance computing need revitalizing? Citing HPC server revenue projections from InterSect 360, Rattner noted that the trend showed a modest compounded annual growth rate (CAGR) of 3.6 percent into the foreseeable feature. “This is not a healthy business,” he complained. Of course, 3.6 percent is pretty healthy growth for some sectors, but for high-flying Silicon Valley chip vendors, apparently not good enough.
Rattner’s answer to HPC server woes is the invention of the 3D Web, a cloud platform which encompasses real-time simulations, multi-view animation, and immersive virtual environments. The idea is that the computational horsepower needed to accomplish this requires high performance computing technology, but the application set extends far beyond traditional HPC. For example, consumer applications like advanced multiplayer online games and virtual communities could help to make the 3D Web a mainstream computing platform.
Industrial applications, like apparel design, would also be able to take advantage of these capabilities. Rattner brought on Shenlei Winkler, the CEO of the Fashion Research Institute, who noted that the $1.7 trillion apparel industry is barely computerized, relying mostly on sketches and physical sampling to design fashion products. She went on to explain how her organization uses OpenSim, an open source virtual world, to slash design time by 75 percent and sample costs by 65 percent. With a more sophisticated 3D Web capability, consumers themselves will be able to design and order clothes. What she didn’t mention was that the trillion-dollar fashion industry would most likely shrink dramatically if this level of sophistication was available to fashion designers and consumers, given that a lot of human labor would be replaced by software.
Rattner also talked with Utah State biology researcher Aaron Duffy, who has created a simulation of a fern ecosystem. The trick here was that Duffy conversed with Rattner as an avatar that was surrounded in his virtual fern forest. The platform he used was called ScienceSim, a virtual world designed as sort of a Second Life for scientists.
This is all first-generation technology. The avatars look cartoonish, and the interactions between them and their virtual environments are limited. The goal, of course, is to provide much more refined visualization and enable a lot greater complexity in these virtual worlds. At one point, Rattner demonstrated a high-res simulation of cloth draped being across a surface. Another simulation of running water included its own sound based solely on the physics of the model. The problem is that these were replays of simulations that took hours to produce on a small cluster. To get to an interactive 3D Web experience, real-time simulations are required.
While giving a nod to his company’s Nehalem chips and even the latest GPUs as evidence of how performance is forging ahead on general-purpose chips, the real point of this exercise was to show how Intel’s upcoming Larrabee processors might fit into this story. What Rattner presented was a system in which Larrabee is attached as an accelerator to act as the heavy-duty computational engine, presumably for 3D Web duty. This is essentially the same model AMD and NVIDIA are using for their GPGPUs, where the GPU and CPU converse via the PCI bus. Apparently though, Intel thinks it can do an end-around the PCI bus and have the CPU and Larrabee talk directly through a “shared virtual memory” to allow for seamless data sharing.
There’s no evidence that Intel has built such a system, but Rattner did apparently have a Larrabee chip on hand to put it through its paces. Running SGEMM, a general matrix multiply subroutine in the Basic Linear Algebra Subprograms (BLAS) library, Larrabee delivered about 800 gigaflops, and just over 1 teraflop when they overclocked it. Keep in mind though, SGEMM is the single precession floating point version of the general matrix multiplication routine. A more modest 8 gigaflops was delivered by Larrabee on a couple of sparse matrix codes (QCD and FEM_CANT).
Considering Larrabee was being positioned strictly for graphics/visualization apps, the scientific benchmarking demo and the whole idea of associating the technology with HPC is yet another example of Intel’s split personality when it comes to this chip. It’s possible that NVIDIA’s recent Fermi GPU rollout has caused Intel to rethink its Larrabee strategy. In any case, when the first Larrabee products are released into the wild next year, we’ll know the answer.