Orlando, Florida — Y2K II? No, not another, surely?

Yes, there is a second Y2K issue. Not the familiar doomsday problem, but, for vendors of high-end computer machinery, more important — and more persistent.

This is the question of the choice and deployment of microprocessors during the next two to five or six years. Through a chance intersection of the calendar and the silicon cycle, the forthcoming microprocessor crisis happens to straddle the year 2000.

The Cray division of Silicon Graphics is pursuing a solution to Y2K II that is both nostalgic and daring. SGI/Cray is embarking on a hop, skip, and jump composed of SGI’s traditional MIPS processors, an inflight adjustment to Intel’s IA-64 (Merced) chips and then a later leap to a distinctive set of scalable vector processors.

Vector processors? Yes. In an attempt at a blitzkrieg around the Y2K II dilemma, SGI/Cray hopes that each vector processor in its projected SV-2 machines will have a rated horsepower of ten GFLOPS.

When will this phenomenon take place? William White, the Cray systems manager at SGI, told HPCwire that the SV-2 should emerge somewhere in 2002 or thereabouts, but not as late as 2005.

CONSEQUENTIAL CHOICES

Microprocessor dilemmas are nothing new. Like the selection of royal brides in the days when monarchy was more than just another form of showbiz, the choice of a microprocessor has always had enduring consequences, including the implications for alliances and sovereignty over coveted territory.

The Y2K II crisis is complicated because it coincides with the slow fading of the boundaries between the PC universe and the constellation of Unix workstations and servers. This process is illuminated by the decision of Intel, the Holy Silicon Emperor, to contract marital alliances in both domains.

Unfortunately, Intel’s IA-64 is turning out to be a rather unformidable prince.

Nevertheless, its paternity commands respect.

For Silicon Graphics, which seeks to govern the stubborn Cray fief in Minnesota as well as its virtual vineyards in California, charting a microprocessor strategy has been especially difficult. SGI has a long relationship with the cadet branch of its family, the MIPS clan of microprocessors.

SGI announced in October that it plans to develop new systems in its ccNUMA Origin line that are to be capable of teraflop performance by the year 2000. These machines will start out with the latest version of the MIPS microprocessor. Switchovers would later take place in which SGI describes as “straightforward, module swap upgrades to IA-64. These high-end servers will deliver an unprecedented teraflop of compute performance and a terabyte of memory in a single shared-memory system.”

White told HPCwire that he expects that SGI will be among the first adapters of the IA-64.

At first glance, the following move to the scalable vector SV-2 would be a very expensive development project for a market that, White acknowledges, is significant but limited.

He explains that SGI/Cray will dodge a large part of the SV-2’s development expense by building it upon the cc-NUMA infrastructure. The Cray crew will be able to focus their energies — and R&D budget — on a new CMOS vector microprocessor that will adopt the characteristic 21st century features: and extremely large number of transistors, extremely slender separations among devices on the chip, a very high clock speed, and so on.

Thus, for its highest tier of products, SGI/Cray would not be dependent on the Merced or its planned successor, code-named McKinley.

BIG QUESTIONS

SGI/Cray nevertheless will confront several big questions.

Will the market be sufficient?

Conversations in the halls and lobbies at SC 98 here in Orlando reveal a surgelet of nostalgia for vector processing. Parallel processing has come a long way since the first IEEE/ACM supercomputing conference here in 1988, but this progress has also exposed the shortcomings of parallelism.

After all, White points out, scientific applications tend to have lots of loops, vectors are the best way to deal with loops. In addition, some important government applications have retained their appetite for vectors.

Persuasive, perhaps, but will that demand be enough to pay for an expensive new microprocessor arcitecture?

Will SGI/Cray be able to finish this venture in time? A target date of 2002 sounds good, but who knows what the competition will be able to bring to the market by, say, 2004?

Finally, will SGI continue to provide adequate funding and understanding support for this distinctively Cray project? After all, SGI is coping with problems of its own.

In any event, SGI/Cray deserves respect as well as skepticism. A whole-hearted vector entry in the Y2K II competition could be a useful stimulus to the entire HPC community.

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Norris Parker Smith is a journalist who specializes in HPC and high bandwidth communications. Reader comments are welcome.