Berkeley Lab’s John Shalf Ponders the Future of HPC Architectures

By Kathy Kincade

June 27, 2019

Editor’s note: Ahead of John Shalf’s well-attended and well-received “high-bandwidth” keynote at ISC 2019, Shalf discussed the talk’s major themes in an interview with Berkeley Lab’s Kathy Kincade. 

What will scientific computing at scale look like in 2030? With the impending demise of Moore’s Law, there are still more questions than answers for users and manufacturers of HPC technologies as they try to figure out what their next best investments should be. As he prepared to head to ISC19 in Frankfurt, Germany, to give a keynote address on the topic, John Shalf – who leads the Computer Science Department in Lawrence Berkeley National Laboratory’s Computational Research Division – shared his thoughts on what the future holds for computing technologies and architectures in the era beyond exascale. ISC took place June 16-20; Shalf’s keynote was on Tuesday, June 18.

What was the focus of your keynote at ISC?

What the landscape of computing, in general, is going to look like after the end of Moore’s Law. We’ve come to depend on Moore’s Law and to really expect that every generation of chips will double the speed, performance, and efficiency of the previous generation. Exascale will be the last iteration of Moore’s Law before the bottom drops out – and the question then is, how do we continue? Is exascale the last of its kind, or are we going to embark on a first-of-its-kind machine for the future of computing?

How long have you been thinking/talking about what’s next for HPC after Moore’s Law?

Where we are now is really the second shoe dropping. I got involved in the Exascale Computing Initiative discussions back in 2008, but actually, my interest in this predates exascale. Back in 2005, David Patterson’s group at UC Berkeley was talking about it in the Parallel Computing Laboratory, and we spent two years there in discussion and debate about the end of  Dennard’s scaling. Ultimately we published “The Landscape of Parallel Computing Research: A View from Berkeley,” which was the prediction that parallel computing would become ubiquitous on account of clock frequencies no longer scaling at exponential rates. This was followed closely by the DARPA 2008 Exascale report that set the stage for the Exascale Initiative for HPC. So the end of Dennard’s scaling was the first shoe to drop, but we always knew that the second shoe would drop fairly soon after the first. And the second shoe dropping means we can’t shrink transistors at all anymore, and that is the real end of Moore’s Law. Exascale is addressing the mass parallelism from the first shoe dropping, and I’ve been concerned about the second shoe dropping during the entire 10-year ramp-up to the Exascale Computing Initiative and subsequent Project, as were many others who were involved in writing the View from Berkeley report and the DARPA 2008 report.

How is the slowing of Moore’s Law already affecting HPC technologies and the industry itself?

We are seeing already procurement cycles stretching out so that the replacement of machines is happening at a slower pace than it has historically. Eric Strohmaier at Berkeley Lab has been tracking the replacement rate on the TOP500 very closely, and he has seen a noticeable slowdown in system replacement rates. I’ve also heard from our colleagues in industry that this is a troubling development that will affect their business model in the future. But we are also seeing these effects in the mega datacenter space, such as Google, Facebook, and Amazon. Google has actually taken to designing its own chips, specialized for particular parts of their workflow, such as the Tensor Processing Unit (TPU). We will probably see even more specialization in the future, but how this applies to HPC is less clear at this point – and that’s what I would like to get people thinking about during my keynote.

Is the lithography industry experiencing a parallel paradigm shift?

Yes, the lithography industry is also being affected, and something’s going to need to change in the economics for that industry. What we have seen in the past decade is that we’ve gone from nearly a dozen leading-edge fabs down to two. Global Foundries recently dropped out as a leading-edge fab, and Intel has had a huge amount of trouble getting its 10nm fab line off the ground. So clearly there are huge tectonic shifts happening in the lithography market as we speak, and how that will resolve itself ultimately remains unclear.

Do we have to start imagining an entirely new computing technology development and production process?

I think the way in which we select and procure systems is going to have to be revisited. While using user application codes to run benchmarks to assess the performance and usability of emerging systems is a great way for us to select systems today that use general purpose processors, it doesn’t seem to be a very good approach for selecting systems that might have specialized features for science. In the future, we need to be more closely involved in the design of the machines with our suppliers to deliver machines that are truly effective for scientific workloads. This is as much about sustainable economic models as it is a change in the design process. The most conventional or even the most technologically elegant solution might not survive, but the one that makes a lot of money will. But our current economic model is breaking.

Looking ahead, I see three paths going forward. The first is specialization and better packaging – specialization meaning designing a machine for a targeted class of applications. This has already been demonstrated in the successful case of the Google TPU, for example. So that is the most immediate path forward.

Another potential path forward is new transistor technology that replaces CMOS that is much more energy efficient and scalable. However, we know from past experience that it takes about 10 years to get from a lab demo to a production product. There are promising candidates, but no clear replacements demonstrated in the lab, which means we are already 10 years too late for that approach to be adopted by time Moore’s Law fails. We need to dramatically accelerate the discovery process in that area through a much more comprehensive materials-to-systems co-design process.

The third approach is to explore alternative models of computation such as quantum and neuromorphic and other, related approaches. These are all fantastic, but they are really expanding computing into areas where digital computing performs very poorly. They aren’t necessarily replacement technologies for digital general purpose computing; they are merely expanding into areas where digital isn’t very effective to start with. So I think these are worthy investments, but they aren’t the replacement technology. They will have a place, but how broadly applicable they will be is still being explored.

What about the development of new chip materials – what role might they play in the future of HPC architectures?

New materials are definitely part of the CMOS replacement. It’s not just new materials; fundamental breakthroughs in solid-state physics will be required to create a suitable CMOS replacement. The fundamental principle of operation for existing transistor technology cannot be substantially improved beyond what we see today. So to truly realize a CMOS replacement will require a new physical principle for switching, whether electrical, optical, or magnetic switching. A fundamentally new physical principle will need to be discovered and that, in turn, will require new materials and new material interfaces to realize effective and manufacturable solutions.

Are there any positives when you look at what is happening in this field right now?

Yes, definitely there are positives. We believe the co-design processor is going to require not just software and hardware people to collaborate, it is going to require this collaboration to go all the way down into the materials and materials physics level. And for the national laboratories, this is a great opportunity for us to work closely with our colleagues in the materials science divisions of our respective laboratories. I work at a national laboratory because I’m excited by cross-disciplinary collaboration, and clearly, that is the only way we are going to make forward progress in this area. The recent ASCR Extreme Heterogeneity and DOE Microelectronics BRNs show strong interest by DOE in this deep co-design and collaborative research that is really needed in this space. So to that extent, it is kind of an exciting time.

When you think about the future of HPC and supercomputing architectures and technologies, what do you imagine they will look like 10 years from now?

I think we’re going to have smaller machines that are more effective for the workflows they target. For three decades we have become used to ever-growing, larger and larger machines, but that doesn’t seem to be the winning approach for creating effective science in the post-exascale and post-Moore era.


About the Author

Kathy Kincade is a science & technology writer and editor with the Berkeley Lab Computing Sciences Communications Group.


Article courtesy Berkeley Lab; Feature image credit: ISC High Performance.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industy updates delivered to you every week!

IBM Unveils Latest Achievements in AI Hardware

December 13, 2019

“The increased capabilities of contemporary AI models provide unprecedented recognition accuracy, but often at the expense of larger computational and energetic effort,” IBM Research wrote in a blog post. “Therefor Read more…

By Oliver Peckham

Focused on ‘Silicon TAM,’ Intel Puts Gary Patton, Former GlobalFoundries CTO, in Charge of Design Enablement

December 12, 2019

Change within Intel’s upper management – and to its company mission – has continued as a published report has disclosed that chip technology heavyweight Gary Patton, GlobalFoundries’ CTO and R&D SVP as well a Read more…

By Doug Black

Quantum Bits: Rigetti Debuts New Gates, D-Wave Cuts NEC Deal, AWS Jumps into the Quantum Pool

December 12, 2019

There’s been flurry of significant news in the quantum computing world. Yesterday, Rigetti introduced a new family of gates that reduces circuit depth required on some problems and D-Wave struck a deal with NEC to coll Read more…

By John Russell

How Formula 1 Used Cloud HPC to Build the Next Generation of Racing

December 12, 2019

Formula 1, Rob Smedley explained, is maybe the biggest racing spectacle in the world, with five hundred million fans tuning in for every race. Smedley, a chief engineer with Formula 1’s performance engineering and anal Read more…

By Oliver Peckham

RPI Powers Up ‘AiMOS’ AI Supercomputer

December 11, 2019

Designed to push the frontiers of computing chip and systems performance optimized for AI workloads, an 8 petaflops (Linpack) IBM Power9-based supercomputer has been unveiled in upstate New York that will be used by IBM Read more…

By Doug Black

AWS Solution Channel

Making High Performance Computing Affordable and Accessible for Small and Medium Businesses with HPC on AWS

High performance computing (HPC) brings a powerful set of tools to a broad range of industries, helping to drive innovation and boost revenue in finance, genomics, oil and gas extraction, and other fields. Read more…

IBM Accelerated Insights

GPU Scheduling and Resource Accounting: The Key to an Efficient AI Data Center

[Connect with LSF users and learn new skills in the IBM Spectrum LSF User Community!]

GPUs are the new CPUs

GPUs have become a staple technology in modern HPC and AI data centers. Read more…

At SC19: Developing a Digital Twin

December 11, 2019

In the not too distant future, we can expect to see our skies filled with unmanned aerial vehicles (UAVs) delivering packages, maybe even people, from location to location. In such a world, there will also be a digital twin for each UAV in the fleet: a virtual model that will follow the UAV through its existence, evolving with time. Read more…

By Aaron Dubrow

Focused on ‘Silicon TAM,’ Intel Puts Gary Patton, Former GlobalFoundries CTO, in Charge of Design Enablement

December 12, 2019

Change within Intel’s upper management – and to its company mission – has continued as a published report has disclosed that chip technology heavyweight G Read more…

By Doug Black

Quantum Bits: Rigetti Debuts New Gates, D-Wave Cuts NEC Deal, AWS Jumps into the Quantum Pool

December 12, 2019

There’s been flurry of significant news in the quantum computing world. Yesterday, Rigetti introduced a new family of gates that reduces circuit depth require Read more…

By John Russell

RPI Powers Up ‘AiMOS’ AI Supercomputer

December 11, 2019

Designed to push the frontiers of computing chip and systems performance optimized for AI workloads, an 8 petaflops (Linpack) IBM Power9-based supercomputer has Read more…

By Doug Black

At SC19: Developing a Digital Twin

December 11, 2019

In the not too distant future, we can expect to see our skies filled with unmanned aerial vehicles (UAVs) delivering packages, maybe even people, from location to location. In such a world, there will also be a digital twin for each UAV in the fleet: a virtual model that will follow the UAV through its existence, evolving with time. Read more…

By Aaron Dubrow

Intel’s Jim Clarke on its New Cryo-controller and why Intel isn’t Late to the Quantum Party

December 9, 2019

Intel today introduced the ‘first-of-its-kind’ cryo-controller chip for quantum computing and previewed a cryo-prober tool for characterizing quantum proces Read more…

By John Russell

On the Spack Track @SC19

December 5, 2019

At the annual supercomputing conference, SC19 in Denver, Colorado, there were Spack events each day of the conference. As a reflection of its grassroots heritage, nine sessions were planned by more than a dozen thought leaders from seven organizations, including three U.S. national Department of Energy (DOE) laboratories and Sylabs... Read more…

By Elizabeth Leake

Intel’s New Hyderabad Design Center Targets Exascale Era Technologies

December 3, 2019

Intel's Raja Koduri was in India this week to help launch a new 300,000 square foot design and engineering center in Hyderabad, which will focus on advanced com Read more…

By Tiffany Trader

AWS Debuts 7nm 2nd-Gen Graviton Arm Processor

December 3, 2019

The “x86 Big Bang,” in which market dominance of the venerable Intel CPU has exploded into fragments of processor options suited to varying workloads, has n Read more…

By Doug Black

Using AI to Solve One of the Most Prevailing Problems in CFD

October 17, 2019

How can artificial intelligence (AI) and high-performance computing (HPC) solve mesh generation, one of the most commonly referenced problems in computational engineering? A new study has set out to answer this question and create an industry-first AI-mesh application... Read more…

By James Sharpe

D-Wave’s Path to 5000 Qubits; Google’s Quantum Supremacy Claim

September 24, 2019

On the heels of IBM’s quantum news last week come two more quantum items. D-Wave Systems today announced the name of its forthcoming 5000-qubit system, Advantage (yes the name choice isn’t serendipity), at its user conference being held this week in Newport, RI. Read more…

By John Russell

DARPA Looks to Propel Parallelism

September 4, 2019

As Moore’s law runs out of steam, new programming approaches are being pursued with the goal of greater hardware performance with less coding. The Defense Advanced Projects Research Agency is launching a new programming effort aimed at leveraging the benefits of massive distributed parallelism with less sweat. Read more…

By George Leopold

Ayar Labs to Demo Photonics Chiplet in FPGA Package at Hot Chips

August 19, 2019

Silicon startup Ayar Labs continues to gain momentum with its DARPA-backed optical chiplet technology that puts advanced electronics and optics on the same chip Read more…

By Tiffany Trader

SC19: IBM Changes Its HPC-AI Game Plan

November 25, 2019

It’s probably fair to say IBM is known for big bets. Summit supercomputer – a big win. Red Hat acquisition – looking like a big win. OpenPOWER and Power processors – jury’s out? At SC19, long-time IBMer Dave Turek sketched out a different kind of bet for Big Blue – a small ball strategy, if you’ll forgive the baseball analogy... Read more…

By John Russell

Cray, Fujitsu Both Bringing Fujitsu A64FX-based Supercomputers to Market in 2020

November 12, 2019

The number of top-tier HPC systems makers has shrunk due to a steady march of M&A activity, but there is increased diversity and choice of processing compon Read more…

By Tiffany Trader

Crystal Ball Gazing: IBM’s Vision for the Future of Computing

October 14, 2019

Dario Gil, IBM’s relatively new director of research, painted a intriguing portrait of the future of computing along with a rough idea of how IBM thinks we’ Read more…

By John Russell

Kubernetes, Containers and HPC

September 19, 2019

Software containers and Kubernetes are important tools for building, deploying, running and managing modern enterprise applications at scale and delivering enterprise software faster and more reliably to the end user — while using resources more efficiently and reducing costs. Read more…

By Daniel Gruber, Burak Yenier and Wolfgang Gentzsch, UberCloud

Leading Solution Providers

SC 2019 Virtual Booth Video Tour

AMD
AMD
CEJN
CJEN
DDN
DDN
MELLANOX
MELLANOX
ONE STOP SYSTEMS
ONE STOP SYSTEMS
PANASAS
PANASAS
SIX NINES IT
SIX NINES IT
VERNE GLOBAL
VERNE GLOBAL
WEKAIO
WEKAIO

Intel Debuts New GPU – Ponte Vecchio – and Outlines Aspirations for oneAPI

November 17, 2019

Intel today revealed a few more details about its forthcoming Xe line of GPUs – the top SKU is named Ponte Vecchio and will be used in Aurora, the first plann Read more…

By John Russell

Dell Ramps Up HPC Testing of AMD Rome Processors

October 21, 2019

Dell Technologies is wading deeper into the AMD-based systems market with a growing evaluation program for the latest Epyc (Rome) microprocessors from AMD. In a Read more…

By John Russell

SC19: Welcome to Denver

November 17, 2019

A significant swath of the HPC community has come to Denver for SC19, which began today (Sunday) with a rich technical program. As is customary, the ribbon cutt Read more…

By Tiffany Trader

When Dense Matrix Representations Beat Sparse

September 9, 2019

In our world filled with unintended consequences, it turns out that saving memory space to help deal with GPU limitations, knowing it introduces performance pen Read more…

By James Reinders

Cerebras to Supply DOE with Wafer-Scale AI Supercomputing Technology

September 17, 2019

Cerebras Systems, which debuted its wafer-scale AI silicon at Hot Chips last month, has entered into a multi-year partnership with Argonne National Laboratory and Lawrence Livermore National Laboratory as part of a larger collaboration with the U.S. Department of Energy... Read more…

By Tiffany Trader

With the Help of HPC, Astronomers Prepare to Deflect a Real Asteroid

September 26, 2019

For years, NASA has been running simulations of asteroid impacts to understand the risks (and likelihoods) of asteroids colliding with Earth. Now, NASA and the European Space Agency (ESA) are preparing for the next, crucial step in planetary defense against asteroid impacts: physically deflecting a real asteroid. Read more…

By Oliver Peckham

Jensen Huang’s SC19 – Fast Cars, a Strong Arm, and Aiming for the Cloud(s)

November 20, 2019

We’ve come to expect Nvidia CEO Jensen Huang’s annual SC keynote to contain stunning graphics and lively bravado (with plenty of examples) in support of GPU Read more…

By John Russell

IBM Opens Quantum Computing Center; Announces 53-Qubit Machine

September 19, 2019

Gauging progress in quantum computing is a tricky thing. IBM yesterday announced the opening of the IBM Quantum Computing Center in New York, with five 20-qubit Read more…

By John Russell

  • arrow
  • Click Here for More Headlines
  • arrow
Do NOT follow this link or you will be banned from the site!
Share This