Consider the GPU. An island of SIMD greatness that makes light work of matrix math. Originally designed to rapidly paint dots on a computer monitor, it was then found to be quite useful in large numbers by HPC practitioners. Enter GenAI, and now these little matrix mavens are in huge demand, so much so that we call it the GPU Squeeze.

The well-known and dominant market leader, Nvidia, has charted much of the pathway for GPU technology. For HPC, GenAI, and a raft of other applications, connecting GPUs provides a way to solve bigger problems and improve your application’s performance.

There are three basic ways to “connect” GPUs.

1. The PCI Bus: A standard server can usually support 4-8 GPUs across the PCI bus. This number can be increased to 32 by using technology like the GigaIO FabreX memory fabric. CXL also shows promise however, Nvidia support is thin. For many applications, these composable GPU domains represent an alternative to the GPU-to-GPU scale-up approach mentioned below.

2. Server-to-Server Interconnect: Ethernet or InfiniBand can connect servers that contain GPUs. This connection level is usually called scale-out, where faster multi-GPU domains are connected by slower networks to form large computational networks. Ethernet has been the workhorse of computer networking since bits started moving between machines. Recently, the specification has been pushed to deliver high performance by introducing the Ultra Ethernet Consortium.  Indeed, Intel has planted its interconnect flag on the Ethernet hill now that the Intel Gaudi -2 AI processor has 24x 100-Gigabit Ethernet connections on the die.

Absent from the Ultra Ethernet Consortium is Nvidia because they basically have sole ownership of the high-performance InfiniBand interconnect market after they purchased Mellanox in March of 2019. The Ultra Ethernet Consortium is designed to be everyone else’s “InfiniBand.” And to be clear Intel used to carry the InfiniBand banner.

3. GPU to GPU Interconnect: Recognizing the need for a fast and scalable GPU connection, Nvidia created NVLink, a GPU-to-GPU connection that can currently transfer data at 1.8 terabytes per second between GPUs. There is also an NVLink rack-level Switch capable of supporting up to 576 fully connected GPUs in a non-blocking compute fabric. GPUs connected via NVLink are called “pods” to indicate they have their own data and computational domain.

As far as everyone else, there are no options other than the AMD Infinity Fabric used to connect MI300A APUs. Similar to the InfiniBand/Ethernet situation, some kind of “Ultra” consortium of competitors is needed to fill the non-Nvidia “pod void.” And that is just what has happened.

AMD, Broadcom, Cisco, Google, Hewlett Packard Enterprise (HPE), Intel, Meta, and Microsoft announced they have aligned to develop a new industry standard dedicated to advancing high-speed and low-latency communication for scale-up AI Accelerators.

Called the Ultra Accelerator Link (UALink), this initial group will define and establish an open industry standard that will enable AI accelerators to communicate more effectively. By creating an interconnect based upon open standards (read this as “not Nvidia”), UALink will enable system OEMs, IT professionals, and system integrators to create a pathway for easier integration, greater flexibility, and scalability of their AI-connected data centers.

Driving Scale-Up for AI Workloads

Similar to NVLink, it is critical to have a robust, low-latency, and efficient scale-up network that can easily add computing resources to a single instance (.i.e., treat GPUs and accelerators as one big system or “pod”).

This is where UALink and an open industry specification become critical to standardizing the interface for AI and Machine Learning, HPC, and Cloud applications for the next generation of hardware. The group will develop a high-speed, low-latency interconnect specification for scale-up communications between accelerators and switches in AI computing pods.

The 1.0 specification will enable the connection of up to 1,024 accelerators within an AI computing pod and allow for direct loads and stores between the memory attached to accelerators, such as GPUs, in the pod. The UALink Promoter Group has formed the UALink Consortium and expects it to be incorporated in Q3 of 2024. The 1.0 specification is expected to be available in Q3 of 2024 and made available to companies that join the Ultra Accelerator Link (UALink) Consortium.

Competition Makes for Strange Bedfellows

The dominance of Nvidia is clearly demonstrated by driving competitors AMD, Intel, and Broadcom to form a Consortium. In particular, in the past, Intel has often taken the “play it alone” strategy when it comes to new technology. In this case, the crushing dominance of Nvidia has been the main motivation for all the Consortium members.

As announced, the Ultra Accelerator Link will be an open standard. This decision should help bring it to market faster as there will be less IP to haggle over, but an optimistic 2026 release still seems rather far off, given the need for massive AI GPU matrix engines yesterday.

In support of the UALink effort J Metz, Ph.D., Chair of the Ultra Ethernet Consortium (UEC) shared his enthusiasm,  “In a very short period of time, the technology industry has embraced challenges that AI and HPC have uncovered. Interconnecting accelerators like GPUs requires a holistic perspective when seeking to improve efficiencies and performance. At UEC, we believe that UALink’s scale-up approach to solving pod cluster issues complements our own scale-out protocol, and we are looking forward to collaborating together on creating an open, ecosystem-friendly, industry-wide solution that addresses both kinds of needs in the future.”