Europe to Dish out €270 Million to Build RISC-V Hardware and Software

By Agam Shah

December 16, 2022

The European Union will release €270 million in funds as it tries to attain technology independence by building chips based on the open RISC-V instruction set architecture.

The EuroHPC Joint Undertaking (EuroHPC JU) has published an upcoming call for proposals to fund a project targeted at building high-performance computers based on RISC-V hardware and software. Proposals will be accepted from January 26, 2023, through April 4, 2023.

“This is exciting … because it’s serious money. There is going to be €270 million associated with this project,” said John Davis, director at the laboratory for open computer architecture at the Barcelona Supercomputing Center, in a presentation this week at the RISC-V Summit, which is being held in Santa Clara, California.

EuroHPC JU last week announced that it would publish a call for proposals on Dec. 16 [PDF], but had not revealed the amount it would award.

The funding will also go toward identifying applications, porting code and developing the RISC-V ecosystem. It will also look forward to a chiplet-based approach so RISC-V CPUs can be paired with accelerators in a single chip package.

This is a big commitment by the European Union to create a computing infrastructure based on RISC-V, which is an open instruction set architecture. RISC-V is free to license and has just a handful of instructions in the base architecture. Chip designs can tack on custom modules and accelerators.

Europe is building a native RISC-V chip to cut reliance on proprietary x86 and Arm architectures. The European Commission has also passed the European Chips Act to boost its computing infrastructure, and has referenced RISC-V multiple times in the legislation.

Academic institutions in Europe have built experimental systems with a patchwork of RISC-V developer boards. Users can access the SUPER-V RISC-V system at BSC or the ExCALIBUR RISC-V system at hosted by the University of Edinburgh.

BSC, Cineca and the University of Bologna were involved in the development of Monte Cimone, a high-performance computer based on the RISC-V architecture. The cluster has eight computing nodes – each with a SiFive U740 chip – in four blades.

The European Processor Initiative has developed RISC-V vector and machine-learning accelerators that will be on exascale computers in the coming years. BSC and Intel are jointly designing a supercomputing chip with a RISC-V CPU, but it is more of a lab project.

The financial commitment shows the seriousness to build a made-in-Europe chip. But there are questions around whether the government’s involvement in chip development will pan out.

In the early 1990s, an effort funded by the Dutch and German governments called JESSI (the Joint European Submicron Silicon Initiative) failed to develop S-RAM memory chips after Philips – which was a major IC manufacturer at the time – took losses and withdrew from the effort. The aggregate government funding for the S-RAM project totaled $265 million at the time.

But RISC-V could be on a better footing than previous efforts, with a lot of work already done on software to support the RISC-V architectures.

BSC started experimenting with Arm smartphone chips in computing clusters in 2011, and now Arm processors are powering Fugaku, the world’s second-fastest supercomputer.

BSC had to write the software for the Arm chips in experimental systems, said Davis, who also chairs the international high-performance computing initiatives at RISC-V International, which is responsible for defining the RISC-V ISA.

The RISC-V chip design could be a true hardware-software co-design effort, which could speed up adoption of the architecture, Davis said.

“What we’re driving is this view that Europe can lead the way for this open hardware-software stack,” Davis said.

A lot of Europe’s efforts will trickle down to RISC-V International’s efforts to push the architecture into the HPC ecosystem. The effort will involve the development of verification tools, OS compatibility, compilers and other toolchains in HPC.

The priorities of the HPC group within RISC-V International include 128-bit addressing, software development, accelerators, ISA extensions and compatibility of technologies like Infiniband that are widely used in supercomputing systems.

“All of these things are driving forces to enable RISC-V to be competitive or lead in high-performance computing,” Davis said.

Users can already test software in an open Github repository at https://riscv-test.org/. Users can add a pull request for software and run it through an automated flow to see if it compiles. The system, called Jenkins, works with the GCC and LLVM compilers. The CI/CD flow can also be used internally if users don’t want the test to be public knowledge.

“The first thing that we need to understand about the software ecosystem is does it even work right,” Davis said.

The European Processor Initiative has created a whole software stack of libraries, tools, compilers to support the hardware test beds at European universities.

“If you’re trying to get into more advanced things where you want to have new features or test new ideas, we have opportunities to work on FPGAs with soft cores or emulation through various implementations… with QEMU or those types of things,” Davis said.

Davis also acknowledged that a lot of work remained to make RISC-V viable for HPC. Companies like SiPearl and Intel have said it could be many years until RISC-V breaks through in HPC, which is dominated by x86 and Arm.

Davis said RISC-V was inevitable in HPC, and pointed to a handful of high-performance chip presentations at the RISC-V Summit as a sign of progress.

Ventana Micro Systems and Tenstorrent shared details about RISC-V high-performance computing chips at the summit this week. Esperanto talked about its ET-SoC-1 chip, which has over 1,000 64-bit RISC-V CPU cores, with each core including a 512-bit vector unit.

The ET-SoC-1 chip can be used as a standalone chip or as an AI accelerator that connects to an x86 chip, said Esperanto founder David Ditzel during a presentation at the RISC-V Summit. Ditzel was previously CEO of Transmeta, and chief technology officer at Sun Microsystems.

The chip has a total of 1,093 RISC-V cores, which is broken up into 1,088 low-power processors that run at under 1.0GHz, four high-performance CPUs running at up to 1.5GHz, and one service processor. The chip has 24 billion transistors, and is made on TSMC’s 7-nm process. About 16 processors on PCIe cards can be put together in a 2U server.

“If you look at a typical x86 core today, it might be three to four watts per core. We are only running about 10 milliwatts per core,” Ditzel said, adding the entire chip can operate on an order of about 20 watts.

“I’ve heard… companies talk about going into the datacenter. Here’s an example of a product not being promised, but actually shipping today,” Ditzel said.

Ditzel shared some inferencing benchmarks of the chip versus Intel’s two Sapphire Rapids CPUs and Nvidia’s A100 GPU, for which the values were pulled from ResNet 50 MLPerf benchmarks managed by MLCommons. Chips from Intel and Nvidia scored significantly higher on inferencing, but also consumed much more power, with Esperanto’s RISC-V chip winning on power efficiency. Per watt, Intel’s Sapphire Rapids (which consumed 700 watts of energy) ran 23 inferences per second, Nvidia’s chips (300 watts) ran 132 inferences per second, and Esperanto’s chip ran 158 inferences per second, Esperanto claimed.

“This shows that the simplicity of RISC-V helps us to achieve lower power, but retain all the benefits of general-purpose programming here,” Ditzel said.

Ventana announced its Veyron V1 chip, which has up to 16 RISC-V cores, and can be paired with up to 12 other chips in a cluster to total 192 cores. The cores on each chip run at up to 3.6GHz, and the silicon is destined for manufacturing on TSMC’s 5-nm process.

Ventana plans to double the core count on its next-generation chips, which can then be combined into a larger high-performance computing cluster, said Travis Lanier, the company’s vice president.

Lanier touted the design advantage of RISC-V processors, saying the ability to customize chips by adding custom extensions makes it easier and cheaper to spin up a chip. It could take a year to design RISC-V chips, which is faster than the multiple years it takes to design and validate an x86 or Arm chip.

Tenstorrent talked about its Ascalon RISC-V CPUs, which will be used in a chip code-named Grendel, which will have 128 cores and support DDR4/DDR5 memory. Grendel will be released next year and has specialized AI accelerators, packet processors, S-RAM and access to PCIe and Ethernet for scalability.

The company’s chips can be general-purpose CPUs, but the design flexibility of RISC-V has allowed the company to create interesting topologies for applications like AI, said Wei-han Lien, architecture lead at Tenstorrent, during a presentation.

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