Alice & Bob, the three-year old quantum computing French startup focused on Cat qubits, and researchers from the National Institute for Research in Digital Science and Technology (Inria, France) today reported a new quantum error correction architecture – low-density parity-check (LDPC) codes on cat qubits – to reduce hardware requirements for useful quantum computers.
“This new architecture using LDPC codes and cat qubits could run Shor’s algorithm with less than 100,000 physical qubits, a 200-fold improvement over competing approaches’ 20 million qubit requirement,” said Théau Peronnin, CEO of Alice & Bob, in the official announcement. “Our approach makes quantum computers more realistic in terms of time, cost and energy consumption, demonstrating our continued commitment to advancing the path to impactful quantum computing with error corrected, logical qubits.”
The latest paper is part of a steady stream of new error correction/mitigation research emerging at the start of 2024 and is a hopeful harbinger for the rest of the year. IBM this month published work on a more efficient implementation of magic state distillation for logical qubits. D-Wave recently announced improved error mitigation on its annealing quantum Advantage2 architecture.
“Over 90% of quantum computing value depends on strong error correction, which is currently many years away from meaningful computations,” said Jean-François Bobier, partner and director at the Boston Consulting Group, in the official announcement. “By improving correction by an order of magnitude, Alice & Bob’s combined innovations could deliver industry-relevant logical qubits on hardware technology that is mature today.”
Cat qubits are not new and many others, including AWS for example, are also exploring the technology. Broadly, there are two types of errors that can affect quantum computation: bit-flip (flips between the 0 and 1 state due to noise) and phase-flips (the reversal of parity in the superposition of 0 and 1). Cat qubits suppress bit-flip errors.
Alice & Bob say their latest theoretical work, available on arXiv (LDPC-cat codes for low-overhead quantum computing in 2D), advances previous research on LDPC codes by enabling the implementation of gates as well as the use of short-range connectivity on quantum chips. “The resulting reduction in overhead required for quantum error correction will allow the operation of 100 high-fidelity logical qubits (with an error rate of 10-8) with as little as 1,500 physical cat qubits,” says the company.
Cat qubits alone already enable logical qubit designs that require significantly fewer qubits, says the company, thanks to their inherent protection from bit flip errors. In a previous paper by Alice & Bob and CEA, researchers demonstrated how it would be possible to run Shor’s algorithm with 350,000 cat qubits, a 60-fold improvement over the state-of-the art.
Here’s the abstract from recent paper (slightly reformatted):
“Quantum low-density parity-check (qLDPC) codes are a promising construction for drastically reducing the overhead of fault-tolerant quantum computing (FTQC) architectures. However, all of the known hardware implementations of these codes require advanced technologies, such as long-range qubit connectivity, high-weight stabilizers, or multi-layered chip layouts. An alternative approach to reduce the hardware overhead of fault-tolerance is to use bosonic cat qubits where bit-flip errors are exponentially suppressed by design. In this work, we combine both approaches and propose an architecture based on cat qubits concatenated in classical LDPC codes correcting for phase-flips. We find that employing such phase-flip LDPC codes provides two major advantages.
- “First, the hardware implementation of the code can be realised using short-range qubit interactions in 2D and low-weight stabilizers, which makes it readily compatible with current superconducting circuit technologies.
- “Second, we demonstrate how to implement a fault-tolerant universal set of logical gates with a second layer of cat qubits while maintaining the local connectivity. We conduct a numerical brute force optimisation of these classical codes to find the ones with the best encoding rate for algorithmically relevant code distances. We discover that some of the best codes benefit from a cellular automaton structure. This allows us to define families of codes with high encoding rates and distances.
- “Finally, we numerically assess the performance of our codes under circuit-level noise. Assuming a physical phase-flip error probability ϵ≈1%, our [165+8ℓ,34+2ℓ,22]code family allows to encode 100 logical qubits with a total logical error probability (including both logical phase-flip and bit-flip) per cycle and per logical qubit ϵL≤10−8 on a 758 cat qubit chip.”
Alice & Bob note that “in previously proposed qLDPC codes implementation, most notably IBM’s last year’s paper, long-range qubit connectivity and high-weight stabilizers were required, which represent a daunting technical challenge. In contrast, Alice & Bob’s combined approach of cat qubits with classical LDPC codes allows the use of short-range, local qubit interactions and low-weight stabilizers.”
This simpler architecture, contends Alice & Bob, enables for the first time the implementation of a fault-tolerant set of parallelizable logical gates without additional hardware complexity. Allowing for logical gates is a necessary step for the implementation of quantum algorithms and practical quantum computing altogether.
An important next step, of course, is to actually demonstrate the approach on a physical chip. Just last month, Alice & Bob announced the tape out of a new chip – the 16-qubit quantum processing unit (QPU), Helium 1 – “expected to improve error rates with every qubit added, making it a prototype for the company’s first error-corrected, logical qubit.”
In the paper, the researchers write, “Thanks to the fact that we are considering local codes in 2D, the physical realization of the chip is greatly simplified compared to architectures that use high-encoding rate quantum LDPC codes for standard qubits, which necessarily require long-range connectivity. Here, the codes can be implemented and operated within a single memory layer, with local stabilizers of weight 4, that is, with exactly the same constraints as the surface code that has already been experimentally realized. Note that the locality of the codes alleviates the need for long-range couplers, which are technologically challenging to realize in large-scale architectures.
“To operate the architecture, as discussed in Section IV, it suffices to add a computing layer with repetition codes, which remains simpler than many existing proposals to realize gates on high-rate LDPC codes. A possible way to realize our two-layer architecture is to use flip-chip technology, inspired by semiconductors and successfully adapted to superconducting processors. The two layers are manufactured separately and then joined face-to-face using indium bump-bonds, where the indium establishes a superconducting galvanic connection between the two chips. Alternatively, the technology of TSV (through silicon vias) would also allow for the realization of our architecture (both sides of a chip are metallized and connectivity is established through the substrate). Figure 9 (see below) represents all qubits, including ancillary qubits and routing qubits, and the required connectivity to implement and operate the code (the qubits of the magic state factories of the computing layer are not shown).”
Link to paper, https://arxiv.org/abs/2401.09541