HPCwire: Straight Shooter: A Conversation with 2008 Seymour Cray Award Winner Steve Wallach

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November 17, 2008

Straight Shooter: A Conversation with 2008 Seymour Cray Award Winner Steve Wallach

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Steve Wallach, a supercomputing legend, has participated in all 20 supercomputing shows and will be honored at the 2008 event with IEEE's Seymour Cray Award for his "contribution to high-performance computing through design of innovative vector and parallel computing systems, notably the Convex mini-supercomputer series, a distinguished industrial career and acts of public service."

The Seymour Cray Award, established in 1998 by the IEEE Computer Society Board of Governors, is given each year to individuals whose innovative contributions to high-performance computing systems best exemplify the creative spirit demonstrated by the late Seymour Cray. Steve Wallach will accept the award on November 20 at 1:30 p.m. at SC08. In addition he will give a plenary presentation, "Processor Architecture: Past, Present, Future" on Wednesday, November 19 at 1:30 p.m.

Those who know Steve Wallach know he is never short on opinions, especially when it comes to high performance computing. HPCwire talked to Wallach about everything from the future of HPC to his philosophy on building a successful HPC business.

HPCwire: First of all, congratulations on the award. What's the best thing about winning the Cray award?

Steve Wallach: Everything. This is one of our industry's greatest honors and I am deeply appreciative. To be associated with Seymour Cray, even in name only, is phenomenal. When I was notified, I was speechless. When the Cray 1 was announced, I read every piece of literature I could find on it. Seymour Cray and his designs had an effect on me, from a technical perspective, more than any other single event.

HPCwire: What's the single biggest change you've seen in high-performance computing in the past 20 years?

Wallach: Perhaps the biggest change is the leveling of the uniprocessor performance. For all practical purposes, with the leveling off of clock frequency and memory bandwidth, the performance of ONE processor core has not changed much. Thus, we have multicore and massive parallelism. In fact, if one calculates the memory bandwidth per core (total memory bandwidth divided by the number of cores) it is DECREASING over time (normalized for peak gflops/core). I was a member of several government studies (National Academy of Engineering and Defense Science Board) that highlighted this leveling-off phenomena.

If we can't access the data, we can't operate on the data. This is one reason the industry is looking into ways to create semantically rich instructions. We know we can achieve more compute performance once the data is located within the core's memory/register infrastructure.

HPCwire: You state in your plenary presentation that the past 40 years has taught us that the "system that is easier to program will always win." Why is that?

Wallach: It boils down to two issues: cost of ownership and cost of development. At a recent Los Alamos Conference, it was pointed out that the cost of a programmer for one year is MORE than the cost of acquiring a TERAFLOP (peak performance) system. We need to address the software productivity issue. Of course this is one of the main objectives of DARPA's HPCS (High Productivity Computer Systems) program.

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